18185941. INTEGRATED CIRCUIT DEVICE simplified abstract (Samsung Electronics Co., Ltd.)
Contents
INTEGRATED CIRCUIT DEVICE
Organization Name
Inventor(s)
Moonseung Yang of Suwon-si (KR)
Edward Namkyu Cho of Suwon-si (KR)
INTEGRATED CIRCUIT DEVICE - A simplified explanation of the abstract
This abstract first appeared for US patent application 18185941 titled 'INTEGRATED CIRCUIT DEVICE
Simplified Explanation
The abstract describes an integrated circuit device that includes a fin-type active region, a gate line, and a source/drain region. The source/drain region consists of three layers stacked in a specific order, each doped with a p-type dopant and having different concentrations of germanium (Ge). The second buffer layer covers the surface of the first buffer layer facing the main body layer. The thickness ratio of the side buffer portion to the bottom buffer portion falls within a specific range.
- The integrated circuit device includes a fin-type active region, gate line, and source/drain region.
- The source/drain region is composed of three layers: first buffer layer, second buffer layer, and main body layer.
- Each layer is doped with a p-type dopant and has different concentrations of germanium (Ge).
- The second buffer layer covers the surface of the first buffer layer facing the main body layer.
- The thickness ratio of the side buffer portion to the bottom buffer portion is within a range of about 0.9 to about 1.1.
Potential Applications
This technology can be applied in various fields where integrated circuits are used, such as:
- Electronics manufacturing
- Semiconductor industry
- Mobile devices
- Computers and servers
- Automotive electronics
Problems Solved
The technology addresses the following problems:
- Improving the performance and efficiency of integrated circuits
- Enhancing the conductivity and stability of the source/drain region
- Reducing leakage current and power consumption
- Optimizing the integration of different layers in the device structure
Benefits
The benefits of this technology include:
- Higher performance and efficiency of integrated circuits
- Improved conductivity and stability of the source/drain region
- Reduced leakage current and power consumption
- Enhanced integration and compatibility with existing device structures
Original Abstract Submitted
An integrated circuit (IC) device includes a fin-type active region, a channel region on the fin-type active region, a gate line surrounding the channel region on the fin-type active region, a source/drain region that is adjacent to the gate line on the fin-type active region and has a sidewall facing the channel region, wherein the source/drain region includes a first buffer layer, a second buffer layer, and a main body layer, which are sequentially stacked in a direction away from the fin-type active region, each include a SiGelayer (x≠0) doped with a p-type dopant, and have different Ge concentrations, and the second buffer layer conformally covers a surface of the first buffer layer that faces the main body layer. A thickness ratio of the side buffer portion to the bottom buffer portion is in a range of about 0.9 to about 1.1.
