18178531. MEMORY PACKAGE AND A MEMORY MODULE INCLUDING THE MEMORY PACKAGE simplified abstract (SK hynix Inc.)
Contents
- 1 MEMORY PACKAGE AND A MEMORY MODULE INCLUDING THE MEMORY PACKAGE
- 1.1 Organization Name
- 1.2 Inventor(s)
- 1.3 MEMORY PACKAGE AND A MEMORY MODULE INCLUDING THE MEMORY PACKAGE - A simplified explanation of the abstract
- 1.4 Simplified Explanation
- 1.5 Potential Applications
- 1.6 Problems Solved
- 1.7 Benefits
- 1.8 Potential Commercial Applications
- 1.9 Possible Prior Art
- 1.10 Unanswered Questions
- 1.11 Original Abstract Submitted
MEMORY PACKAGE AND A MEMORY MODULE INCLUDING THE MEMORY PACKAGE
Organization Name
Inventor(s)
Won Ha Choi of Gyeonggi-do (KR)
MEMORY PACKAGE AND A MEMORY MODULE INCLUDING THE MEMORY PACKAGE - A simplified explanation of the abstract
This abstract first appeared for US patent application 18178531 titled 'MEMORY PACKAGE AND A MEMORY MODULE INCLUDING THE MEMORY PACKAGE
Simplified Explanation
The abstract describes a memory package with a package substrate, memory chip, buffer chip, interface data channel buses, and outer data channel buses. The buffer chip receives data from the memory chip and provides it through the outer data channel buses.
- Memory package with memory chip and buffer chip mounted on a package substrate
- M×N interface data channel buses between memory chip and buffer chip
- (M×N)/2 outer data channel buses connected to the buffer chip
- Buffer chip receives data from memory chip through interface data channel buses and provides data through outer data channel buses
Potential Applications
The technology described in the patent application could be applied in:
- High-performance computing systems
- Data centers
- Networking equipment
Problems Solved
- Improved data transfer speeds between memory and buffer chips
- Enhanced data processing capabilities
- Reduced latency in data transmission
Benefits
- Faster data processing
- Increased efficiency in data transfer
- Enhanced overall system performance
Potential Commercial Applications
Optimized Memory Package for High-Speed Data Processing
Possible Prior Art
No prior art known at this time.
Unanswered Questions
How does this technology compare to existing memory package designs in terms of data transfer speeds?
The article does not provide a direct comparison with existing memory package designs to assess the improvement in data transfer speeds.
What are the potential limitations or drawbacks of implementing this technology in practical applications?
The article does not address any potential limitations or drawbacks that may arise from implementing this technology in real-world scenarios.
Original Abstract Submitted
A single memory package includes a package substrate; at least one of a memory chip and a buffer chip mounted on the package substrate; M×N number of interface data channel buses between the memory chip and the buffer chip; and (M×N)/2number of outer data channel buses connected to the buffer chip. The buffer chip receives data from the memory chip through the interface data channel buses, and provides the data through the outer data channel buses. The M, N, and n are natural numbers.
