18176096. POWER REDUCTION IN A CLOCK BUFFER OF A MEMORY MODULE BASED UPON MEMORY MODULE TOPOLOGY simplified abstract (Dell Products L.P.)

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POWER REDUCTION IN A CLOCK BUFFER OF A MEMORY MODULE BASED UPON MEMORY MODULE TOPOLOGY

Organization Name

Dell Products L.P.

Inventor(s)

Isaac Q. Wang of Austin TX (US)

Lee B. Zaretsky of Nazare (PT)

POWER REDUCTION IN A CLOCK BUFFER OF A MEMORY MODULE BASED UPON MEMORY MODULE TOPOLOGY - A simplified explanation of the abstract

This abstract first appeared for US patent application 18176096 titled 'POWER REDUCTION IN A CLOCK BUFFER OF A MEMORY MODULE BASED UPON MEMORY MODULE TOPOLOGY

Simplified Explanation

The clock buffer device described in the abstract is designed to manage clock signals in a memory module efficiently. Here are some key points to explain the patent/innovation:

  • The device includes two phase-locked loops (PLLs) that can be selectively coupled to clock output buffers.
  • The first PLL is connected to the first clock input and can be routed to all clock output buffers.
  • The second PLL is connected to the second clock input and can be selectively disabled, based on system configuration.
  • When the first information handling system provides a clock signal only on the first input, the device disables the second PLL and routes the output of the first PLL to the clock output buffers.

Potential Applications of this Technology: - Memory modules in computer systems - Networking equipment - Communication devices

Problems Solved by this Technology: - Efficient management of clock signals - Reduction of power consumption - Improved synchronization in memory modules

Benefits of this Technology: - Enhanced performance of memory modules - Flexibility in handling different clock signals - Cost-effective solution for clock distribution

Potential Commercial Applications of this Technology: - Memory module manufacturers - Computer hardware companies - Semiconductor industry

Possible Prior Art: - Prior art related to clock buffer devices in memory modules - Previous patents on phase-locked loops in electronic devices

Unanswered Questions: 1. How does the device handle potential signal interference or noise in the clock signals? 2. Are there any limitations to the number of clock output buffers that can be supported by the device?


Original Abstract Submitted

A clock buffer device for a memory module includes a first clock input coupled to an input of a first phase-locked loop (PLL), and a second clock input coupled to an input of a second PLL. An output of the first PLL is selectably coupled to clock output buffers, and an output of the second PLL is selectably coupled to a subset of the clock output buffers. The clock buffer device receives a first indication that a first information handling system is configured to provide a first clock signal on the first clock input but to not provide a second clock signal on the second clock input, and, in response to the indication, couples the output of the first PLL to the clock output buffers and to disables the second PLL.

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