18174865. SEMICONDUCTOR CHIP AND SEMICONDUCTOR PACKAGE INCLUDING THE SAME simplified abstract (Samsung Electronics Co., Ltd.)
Contents
SEMICONDUCTOR CHIP AND SEMICONDUCTOR PACKAGE INCLUDING THE SAME
Organization Name
Inventor(s)
Joongwon Shin of Suwon-si (KR)
SEMICONDUCTOR CHIP AND SEMICONDUCTOR PACKAGE INCLUDING THE SAME - A simplified explanation of the abstract
This abstract first appeared for US patent application 18174865 titled 'SEMICONDUCTOR CHIP AND SEMICONDUCTOR PACKAGE INCLUDING THE SAME
Simplified Explanation
The semiconductor chip described in the patent application has a reduced thickness and improved reliability. It includes a semiconductor substrate, an integrated device layer, a multi-wiring layer, and a pad metal layer with test pads.
- Semiconductor chip with reduced thickness and improved reliability
- Includes semiconductor substrate, integrated device layer, multi-wiring layer, and pad metal layer with test pads
- Test pads are defined in the central portion of the pad metal layer
- Outer portion of the pad metal layer overlaps the wires in a perpendicular direction
- Potential Applications:**
- Semiconductor manufacturing - Electronics industry - Integrated circuit design
- Problems Solved:**
- Reduced thickness of semiconductor chip - Improved reliability of semiconductor chip - Efficient testing process with defined test pads
- Benefits:**
- Enhanced reliability of semiconductor chips - Improved testing capabilities - Potential for smaller and more compact electronic devices
Original Abstract Submitted
Provided are a semiconductor chip with a reduced thickness and improved reliability, and a semiconductor package including the semiconductor chip. The semiconductor chip includes a semiconductor substrate, an integrated device layer on the semiconductor substrate, a multi-wiring layer on the integrated device layer, and a pad metal layer of a plurality of pad metal layers on the multi-wiring layer, and having test pads defined therein. The pad metal layers extend in a first direction parallel to a top surface of the semiconductor substrate or in a second direction perpendicular to the first direction. A test pad is a central portion of the pad metal layer and, and an outer portion of the pad metal layer excluding the test pad overlaps the wires in a third direction perpendicular to the top surface of the semiconductor substrate.
