18170482. FIELD EFFECT TRANSISTOR WITH ISOLATION STRUCTURE AND METHOD simplified abstract (Taiwan Semiconductor Manufacturing Co., Ltd.)

FIELD EFFECT TRANSISTOR WITH ISOLATION STRUCTURE AND METHOD

Organization Name

Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor(s)

Kuan-Ting Pan of Hsinchu (TW)

Kuo-Cheng Chiang of Hsinchu (TW)

Shi Ning Ju of Hsinchu (TW)

Chih-Hao Wang of Hsinchu (TW)

FIELD EFFECT TRANSISTOR WITH ISOLATION STRUCTURE AND METHOD - A simplified explanation of the abstract

This abstract first appeared for US patent application 18170482 titled 'FIELD EFFECT TRANSISTOR WITH ISOLATION STRUCTURE AND METHOD

Simplified Explanation

The patent application describes a device that includes two stacks of nanostructures, with a wall structure between them. The device also includes source/drain regions abutting each stack, and a gate structure that wraps around the nanostructures of the first stack.

• The device has a first stack of nanostructures and a second stack of nanostructures horizontally offset from the first stack.
• There is a wall structure between the first and second stacks, spaced apart from the nanostructures of the first stack.
• The device includes a first source/drain region abutting the first stack of nanostructures and a second source/drain region abutting the second stack of nanostructures.
• The gate structure includes a gate dielectric layer that wraps around the nanostructures of the first stack.
• The gate structure also includes a conductive core layer on the gate dielectric layer.
• The thickness of the conductive core layer between one of the nanostructures of the first stack and the wall structure is in a range of 0 nanometers to 1 nanometer.

Potential Applications:

• This technology could be used in the development of advanced electronic devices, such as transistors or memory cells.
• It may find applications in the field of nanoelectronics and nanotechnology.

Problems Solved:

• The device design addresses the need for improved performance and efficiency in electronic devices.
• It provides a way to control the flow of current through the nanostructures, enhancing the functionality of the device.

Benefits:

• The device design allows for better control and manipulation of the nanostructures, leading to improved device performance.
• It offers the potential for higher integration density and smaller device footprint.
• The technology may enable the development of more efficient and powerful electronic devices.

Original Abstract Submitted

A device includes: a first stack of nanostructures; a second stack of nanostructures horizontally offset from the first stack; a first source/drain region abutting the first stack of nanostructures; a second source/drain region abutting the second stack of nanostructures; a wall structure between the first and second stacks and spaced apart from the nanostructures of the first stack; and a first gate structure, which includes: a gate dielectric layer that wraps around the nanostructures of the first stack; and a conductive core layer on the gate dielectric layer, wherein thickness of the conductive core layer between one of the nanostructure of the first stack and the wall structure is in a range of 0 nanometers to 1 nanometer, inclusive.