18166656. TEST DEVICES AND SYSTEMS THAT UTILIZE EFFICIENT TEST ALGORITHMS TO EVALUATE DEVICES UNDER TEST simplified abstract (SAMSUNG ELECTRONICS CO., LTD.)

TEST DEVICES AND SYSTEMS THAT UTILIZE EFFICIENT TEST ALGORITHMS TO EVALUATE DEVICES UNDER TEST

Organization Name

SAMSUNG ELECTRONICS CO., LTD.

Inventor(s)

Jungmin Bak of Suwon-si (KR)

Junyoung Ko of Suwon-si (KR)

Changhwi Park of Suwon-si (KR)

TEST DEVICES AND SYSTEMS THAT UTILIZE EFFICIENT TEST ALGORITHMS TO EVALUATE DEVICES UNDER TEST - A simplified explanation of the abstract

This abstract first appeared for US patent application 18166656 titled 'TEST DEVICES AND SYSTEMS THAT UTILIZE EFFICIENT TEST ALGORITHMS TO EVALUATE DEVICES UNDER TEST

Simplified Explanation

The patent application describes a test device that is used to determine whether a memory device has a defect. The device includes a power supply circuit and a test controller.

• The power supply circuit supplies an input voltage to the memory device under test through a power voltage pin.
• The test controller performs several functions:

   * It transmits a command signal to the memory device.
   * It measures the first current flowing to the memory device through the power voltage pin at a specific time point after transmitting the command signal.
   * It measures the second current flowing to the memory device through the power voltage pin at a different time point.
   * It compares the measured first current to the measured second current to determine if the memory device has a defect.

Potential applications of this technology:

• Memory device testing in manufacturing processes.
• Quality control in memory device production.
• Troubleshooting and diagnosing memory device issues.

Problems solved by this technology:

• Efficient and accurate testing of memory devices for defects.
• Early detection of defects in memory devices.
• Streamlining the manufacturing process by identifying faulty memory devices.

Benefits of this technology:

• Improved reliability and performance of memory devices.
• Cost savings by identifying and eliminating defective memory devices early in the production process.
• Time savings in testing and troubleshooting memory devices.

Original Abstract Submitted

A test device includes a power supply circuit that is configured to supply an input voltage through a power voltage pin to a memory device under test, and a test controller, which is configured to: (i) transmit a command signal to the memory device, (ii) measure a first current flowing to the memory device through the power voltage pin at a first time point after transmitting the command signal, (iii) measure a second current flowing to the memory device through the power voltage pin at a second time point, which is different from the first time point, and (iv) compare the measured first current to the measured second current to thereby determine whether the memory device has a defect therein.