18165639. NANOSHEET DEVICES AND METHODS OF FABRICATING THE SAME simplified abstract (TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.)
NANOSHEET DEVICES AND METHODS OF FABRICATING THE SAME
Organization Name
TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
Inventor(s)
Chia-Chung Chen of Hsinchu (TW)
Zi-Ang Su of Hsinchu County (TW)
Chung-Sheng Yuan of Hsinchu (TW)
NANOSHEET DEVICES AND METHODS OF FABRICATING THE SAME - A simplified explanation of the abstract
This abstract first appeared for US patent application 18165639 titled 'NANOSHEET DEVICES AND METHODS OF FABRICATING THE SAME
Simplified Explanation
The semiconductor structure described in the patent application includes a substrate with a stack of p-n junction structures embedded in it. The structure also features a semiconductor fin protruding from the substrate, a pair of source/drain structures located in the semiconductor fin, and a gate structure positioned over a channel region of the semiconductor fin between the source/drain structures.
- The semiconductor structure includes a substrate and a stack of p-n junction structures.
- A semiconductor fin protrudes from the substrate.
- A pair of source/drain structures is located in the semiconductor fin.
- A gate structure is positioned over a channel region of the semiconductor fin between the source/drain structures.
Potential Applications
- Semiconductor devices
- Integrated circuits
- Transistors
Problems Solved
- Improved performance of semiconductor devices
- Enhanced integration of components
- Increased efficiency of electronic devices
Benefits
- Higher performance
- Increased integration
- Improved efficiency
Original Abstract Submitted
A semiconductor structure includes a substrate and a stack of p-n junction structures embedded in the substrate. The semiconductor structure includes a semiconductor fin protruding from the substrate. The semiconductor structure includes a pair of source/drain structures disposed in the semiconductor fin. The semiconductor structure includes a gate structure over a channel region of the semiconductor fin and interposed between the pair of source/drain structures.
