18163412. STRUCTURE AND FORMATION METHOD OF PACKAGE WITH HYBRID INTERCONNECTION simplified abstract (TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.)
Contents
- 1 STRUCTURE AND FORMATION METHOD OF PACKAGE WITH HYBRID INTERCONNECTION
- 1.1 Organization Name
- 1.2 Inventor(s)
- 1.3 STRUCTURE AND FORMATION METHOD OF PACKAGE WITH HYBRID INTERCONNECTION - A simplified explanation of the abstract
- 1.4 Simplified Explanation
- 1.5 Potential Applications
- 1.6 Problems Solved
- 1.7 Benefits
- 1.8 Potential Commercial Applications
- 1.9 Possible Prior Art
- 1.10 Original Abstract Submitted
STRUCTURE AND FORMATION METHOD OF PACKAGE WITH HYBRID INTERCONNECTION
Organization Name
TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
Inventor(s)
Tsung-Fu Tsai of Changhua County (TW)
Szu-Wei Lu of Hsinchu City (TW)
Shih-Peng Tai of Xinpu Township (TW)
Chen-Hua Yu of Hsinchu City (TW)
STRUCTURE AND FORMATION METHOD OF PACKAGE WITH HYBRID INTERCONNECTION - A simplified explanation of the abstract
This abstract first appeared for US patent application 18163412 titled 'STRUCTURE AND FORMATION METHOD OF PACKAGE WITH HYBRID INTERCONNECTION
Simplified Explanation
The patent application describes a method for forming a package structure by bonding multiple chip structures on a semiconductor substrate using different bonding techniques and forming a protective layer around the chip structures.
- Metal-to-metal bonding and dielectric-to-dielectric bonding are used to bond the first chip structure on the semiconductor substrate.
- Solder-containing bonding structures are used to bond the second chip structure over the semiconductor substrate.
- A protective layer is formed surrounding the second chip structure, with a portion of it between the semiconductor substrate and the bottom of the second chip structure.
Potential Applications
This technology could be applied in the manufacturing of advanced semiconductor devices, such as microprocessors, memory chips, and sensors.
Problems Solved
This technology solves the problem of efficiently bonding multiple chip structures on a semiconductor substrate while providing protection to the chip structures.
Benefits
The benefits of this technology include improved reliability, enhanced performance, and increased integration density of semiconductor devices.
Potential Commercial Applications
Potential commercial applications of this technology include the production of high-performance electronic devices for various industries, such as telecommunications, automotive, and consumer electronics.
Possible Prior Art
One possible prior art could be the use of different bonding techniques in semiconductor packaging, but the specific combination of metal-to-metal bonding, dielectric-to-dielectric bonding, and solder-containing bonding structures as described in this patent application may be novel.
Unanswered Questions
How does this technology compare to existing semiconductor packaging methods in terms of cost-effectiveness and scalability?
This article does not provide information on the cost-effectiveness and scalability of this technology compared to existing semiconductor packaging methods.
What are the potential challenges or limitations of implementing this technology in mass production?
This article does not address the potential challenges or limitations of implementing this technology in mass production, such as process complexity or compatibility with existing manufacturing equipment.
Original Abstract Submitted
A package structure and a formation method are provided. The method includes providing a semiconductor substrate and bonding a first chip structure on the semiconductor substrate through metal-to-metal bonding and dielectric-to-dielectric bonding. The method also includes bonding a second chip structure over the semiconductor substrate through solder-containing bonding structures. The method further includes forming a protective layer surrounding the second chip structure. A portion of the protective layer is between the semiconductor substrate and a bottom of the second chip structure.
