18162878. SEMICONDUCTOR PACKAGE simplified abstract (SAMSUNG ELECTRONICS CO., LTD.)

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SEMICONDUCTOR PACKAGE

Organization Name

SAMSUNG ELECTRONICS CO., LTD.

Inventor(s)

Yeongkwon Ko of Hwaseong-si (KR)

Un-Byoung Kang of Hwaseong-si (KR)

Jaekyung Yoo of Seoul (KR)

Teak Hoon Lee of Hwaseong-si (KR)

SEMICONDUCTOR PACKAGE - A simplified explanation of the abstract

This abstract first appeared for US patent application 18162878 titled 'SEMICONDUCTOR PACKAGE

Simplified Explanation

The abstract describes a semiconductor package that includes a package substrate, a connection substrate, a semiconductor chip, and connection terminals. The connection substrate has a recession on its lower corner, facing the top surface of the package substrate. The first connection terminals connect the connection substrate to the semiconductor chip, while the second connection terminals connect the package substrate to the connection substrate. The recession is spaced apart from the second connection terminals.

  • The semiconductor package includes a package substrate.
  • The connection substrate is located on the package substrate and has a recession on its lower corner.
  • The recession faces the top surface of the package substrate.
  • A semiconductor chip is mounted on the connection substrate.
  • The first connection terminals connect the connection substrate to the semiconductor chip.
  • The second connection terminals connect the package substrate to the connection substrate.
  • The recession is laterally spaced apart from the second connection terminals.

Potential Applications

  • Semiconductor packaging industry
  • Electronics manufacturing

Problems Solved

  • Provides a structure for connecting a semiconductor chip to a package substrate.
  • Allows for efficient and reliable electrical connections between the components.

Benefits

  • Simplifies the process of connecting a semiconductor chip to a package substrate.
  • Improves the reliability and performance of the semiconductor package.
  • Reduces the risk of electrical failures and damage to the components.


Original Abstract Submitted

A semiconductor package including a package substrate, a connection substrate on the package substrate and having on a lower corner of the connection substrate a recession that faces a top surface of the package substrate, a semiconductor chip on the connection substrate, a plurality of first connection terminals connecting the connection substrate to the semiconductor chip, and a plurality of second connection terminals connecting the package substrate to the connection substrate. The recession is laterally spaced apart from the second connection terminals.