18161859. SEMICONDUCTOR CHIP AND SEQUENCE CHECKING CIRCUIT simplified abstract (TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.)
SEMICONDUCTOR CHIP AND SEQUENCE CHECKING CIRCUIT
Organization Name
TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
Inventor(s)
Shih-Cheng Kao of HSINCHU CITY (TW)
Bi-Yang Li of HSINCHU CITY (TW)
SEMICONDUCTOR CHIP AND SEQUENCE CHECKING CIRCUIT - A simplified explanation of the abstract
This abstract first appeared for US patent application 18161859 titled 'SEMICONDUCTOR CHIP AND SEQUENCE CHECKING CIRCUIT
Simplified Explanation
The semiconductor chip described in the patent application includes a physical layer and a processing circuit. The physical layer contains at least one sequence checking circuit and at least one signal transmission path. The sequence checking circuit generates test result signals based on a clock signal and test data signals transmitted through the signal transmission path, without transmitting the clock signal through the path. The processing circuit, connected to the physical layer, determines the operation status of the signal transmission path based on the voltage level of the test result signals.
- The semiconductor chip includes a physical layer with sequence checking circuits and signal transmission paths.
- The sequence checking circuits generate test result signals based on clock signals and test data signals.
- The processing circuit analyzes the voltage level of the test result signals to determine the operation status of the signal transmission paths.
Potential Applications
- Integrated circuits
- Communication devices
- Data processing systems
Problems Solved
- Ensuring data integrity in signal transmission paths
- Efficient testing of signal sequences
- Improving overall performance and reliability of semiconductor chips
Benefits
- Enhanced data transmission reliability
- Simplified testing processes
- Increased efficiency in semiconductor chip operations
Original Abstract Submitted
A semiconductor chip includes a physical layer and a processing circuit. The physical layer includes at least one sequence checking circuit and at least one signal transmission path, wherein the at least one sequence checking circuit is configured to generate at least one test result signal according to a clock signal and at least one test data signal transmitted through the at least one signal transmission path, and the clock signal is not transmitted through the at least one signal transmission path. The processing circuit is electrically coupled to the physical layer and is configured to determine an operation status of the at least one signal transmission path according to the voltage level of the at least one test result signal.
