18161066. SEMICONDUCTOR PACKAGE simplified abstract (SAMSUNG ELECTRONICS CO., LTD.)
Contents
SEMICONDUCTOR PACKAGE
Organization Name
Inventor(s)
Kyungdon Mun of Hwaseong-si (KR)
Myungsam Kang of Hwaseong-si (KR)
Yieok Kwon of Hwaseong-si (KR)
Jeongseok Kim of Cheonan-si (KR)
Bongju Cho of Hwaseong-si (KR)
SEMICONDUCTOR PACKAGE - A simplified explanation of the abstract
This abstract first appeared for US patent application 18161066 titled 'SEMICONDUCTOR PACKAGE
Simplified Explanation
The abstract describes a semiconductor package that includes a redistribution substrate, a semiconductor chip, a vertical connection structure, and an encapsulant. The vertical connection structure consists of a metal pillar with a roughened surface plating layer on its bottom, top, and side surfaces.
- The semiconductor package includes a redistribution substrate, a semiconductor chip, a vertical connection structure, and an encapsulant.
- The vertical connection structure is adjacent to the semiconductor chip and is electrically connected to the redistribution layer.
- The metal pillar in the vertical connection structure has a roughened surface plating layer on its bottom, top, and side surfaces.
Potential applications of this technology:
- Semiconductor packaging industry
- Electronics manufacturing industry
Problems solved by this technology:
- Provides a reliable and efficient vertical connection structure for semiconductor packages.
- Enhances the electrical connectivity between the semiconductor chip and the redistribution substrate.
Benefits of this technology:
- Improved performance and reliability of semiconductor packages.
- Enhanced electrical connection between the semiconductor chip and the redistribution substrate.
- Increased efficiency in the semiconductor packaging process.
Original Abstract Submitted
A semiconductor package includes a redistribution substrate including a first redistribution layer; a semiconductor chip electrically connected to the first redistribution layer; a vertical connection structure adjacent a periphery of the semiconductor chip and electrically connected to the first redistribution layer; and an encapsulant on the vertical connection structure. The vertical connection structure includes a metal pillar having a bottom surface facing the redistribution substrate, a top surface positioned opposite to the bottom surface, and a side surface positioned between the bottom surface and the top surface. The vertical connection structure further includes a plating layer on each of the bottom surface, the top surface, and the side surface of the metal pillar, and having a roughened surface.
