18156593. MEMORY CELL AND METHOD OF OPERATING THE SAME simplified abstract (TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.)
Contents
MEMORY CELL AND METHOD OF OPERATING THE SAME
Organization Name
TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
Inventor(s)
Sai-Hooi Yeong of Hsinchu (TW)
MEMORY CELL AND METHOD OF OPERATING THE SAME - A simplified explanation of the abstract
This abstract first appeared for US patent application 18156593 titled 'MEMORY CELL AND METHOD OF OPERATING THE SAME
Simplified Explanation
The abstract describes a memory cell that includes a write bit line, a read word line, a write transistor, and a read transistor. The write transistor is connected between the write bit line and a first node, while the read transistor is connected to the write transistor through the first node. The read transistor has a ferroelectric layer, with its drain terminal connected to the read word line and its source terminal connected to a second node. The write transistor is designed to set the stored data value of the memory cell by using a write bit line signal that adjusts the polarization state of the read transistor, which corresponds to the stored data value.
- Memory cell includes write bit line, read word line, write transistor, and read transistor
- Write transistor connects write bit line to first node
- Read transistor connects to write transistor through first node
- Read transistor has a ferroelectric layer
- Drain terminal of read transistor connects to read word line
- Source terminal of read transistor connects to second node
- Write transistor sets stored data value by adjusting polarization state of read transistor using write bit line signal
- Polarization state corresponds to stored data value
Potential Applications
- Memory cells for computer systems
- Non-volatile memory devices
- High-density memory storage
Problems Solved
- Provides a method for setting the stored data value in a memory cell
- Utilizes a ferroelectric layer to adjust the polarization state of the read transistor
Benefits
- Allows for efficient and accurate storage of data in memory cells
- Enables high-density memory storage
- Provides non-volatile memory capabilities
Original Abstract Submitted
A memory cell includes a write bit line, a read word line, a write transistor, and a read transistor. The write transistor is coupled between the write bit line and a first node. The read transistor is coupled to the write transistor by the first node. The read transistor includes a ferroelectric layer, a drain terminal of the read transistor is coupled to the read word line, and a source terminal of the read transistor is coupled to a second node. The write transistor is configured to set a stored data value of the memory cell by a write bit line signal that adjusts a polarization state of the read transistor. The polarization state corresponds to the stored data value.
