18155759. LAYOUT STRUCTURE AND METHOD FOR FABRICATING SAME simplified abstract (Changxin Memory Technologies, Inc.)

LAYOUT STRUCTURE AND METHOD FOR FABRICATING SAME

Organization Name

Changxin Memory Technologies, Inc.

Inventor(s)

Yingdong Guo of Hefei (CN)

Jing Xu of Hefei (CN)

Wei Jiang of Hefei (CN)

Xue Shan of Hefei (CN)

LAYOUT STRUCTURE AND METHOD FOR FABRICATING SAME - A simplified explanation of the abstract

This abstract first appeared for US patent application 18155759 titled 'LAYOUT STRUCTURE AND METHOD FOR FABRICATING SAME

Simplified Explanation

The patent application describes a layout structure and fabrication method for a frequency divider pattern layer and a conductor pattern layer. The frequency divider pattern layer includes four regions arranged centrosymmetrically, while the conductor pattern layer includes two sub-layers.

• The first sub-conductor pattern layer connects the first and second frequency divider regions, as well as the third and fourth frequency divider regions.
• The second sub-conductor pattern layer connects the first and fourth frequency divider regions, as well as the second and third frequency divider regions.

Potential applications of this technology:

• Integrated circuits
• Wireless communication systems
• Signal processing devices

Problems solved by this technology:

• Reduces channel transmission difference between different frequency dividers
• Improves the performance and accuracy of frequency divider structures

Benefits of this technology:

• Enhanced efficiency and reliability of frequency dividers
• Simplified layout structure and fabrication process
• Improved signal processing capabilities

Original Abstract Submitted

Embodiments relates to a layout structure and a method for fabricating the same. A frequency divider pattern layer includes a first frequency divider region, a second frequency divider region, a third frequency divider region and a fourth frequency divider region arranged centrosymmetrically. A conductor pattern layer includes a first sub-conductor pattern layer and a second sub-conductor pattern layer stacked. The first sub-conductor pattern layer is configured to communicate the first frequency divider region with the second frequency divider region, and communicate the third frequency divider region with the fourth frequency divider region. The second sub-conductor pattern layer is configured to communicate the first frequency divider region with the fourth frequency divider region, and communicate the second frequency divider region with the third frequency divider region. The embodiments reduce a channel transmission difference between different frequency dividers in a frequency divider structure.