18154919. SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SAME simplified abstract (SAMSUNG ELECTRONICS CO., LTD.)
Contents
SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SAME
Organization Name
Inventor(s)
Younglyong Kim of Anyang-si (KR)
Myungkee Chung of Hwaseong-si (KR)
SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SAME - A simplified explanation of the abstract
This abstract first appeared for US patent application 18154919 titled 'SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SAME
Simplified Explanation
The abstract describes a semiconductor package that includes a semiconductor chip, an interposer, and a molding layer. The interposer has a heat dissipation pattern that is electrically insulated from the semiconductor chip. The molding layer covers parts of the interposer and the semiconductor chip, but leaves some of the upper surface of the interposer exposed.
- The semiconductor package includes a semiconductor chip, an interposer, and a molding layer.
- The interposer has a heat dissipation pattern that is electrically insulated from the semiconductor chip.
- The heat dissipation pattern includes a through electrode and an upper pad connected to the through electrode.
- The molding layer covers parts of the interposer and the semiconductor chip.
- Some of the upper surface of the interposer is not covered by the molding layer.
Potential applications of this technology:
- Electronics manufacturing industry
- Semiconductor packaging industry
- Consumer electronics industry
Problems solved by this technology:
- Heat dissipation in semiconductor packages
- Electrical insulation between the heat dissipation pattern and the semiconductor chip
Benefits of this technology:
- Improved heat dissipation in semiconductor packages
- Enhanced electrical insulation for better performance and reliability
Original Abstract Submitted
A semiconductor package including a semiconductor chip, an interposer on the semiconductor chip, and a molding layer covering at least a portion of the semiconductor chip and at least a portion of the interposer may be provided. The interposer includes a interposer substrate and a heat dissipation pattern penetrating the interposer substrate and electrically insulated from the semiconductor chip. The heat dissipation pattern includes a through electrode disposed in the interposer substrate and an upper pad disposed on an upper surface of the interposer substrate and connected to the through electrode. The molding layer covers at least a portion of a sidewall of the upper pad and the upper surface of the interposer substrate. At least a portion of an upper surface of the upper pad is not covered by the molding layer.
