18154210. THREE-DIMENSIONAL FLASH MEMORY WITH REDUCED WIRE LENGTH AND MANUFACTURING METHOD THEREFOR simplified abstract (SAMSUNG ELECTRONICS CO., LTD.)
Contents
THREE-DIMENSIONAL FLASH MEMORY WITH REDUCED WIRE LENGTH AND MANUFACTURING METHOD THEREFOR
Organization Name
Inventor(s)
Yun Heub Song of Seongnam-si (KR)
THREE-DIMENSIONAL FLASH MEMORY WITH REDUCED WIRE LENGTH AND MANUFACTURING METHOD THEREFOR - A simplified explanation of the abstract
This abstract first appeared for US patent application 18154210 titled 'THREE-DIMENSIONAL FLASH MEMORY WITH REDUCED WIRE LENGTH AND MANUFACTURING METHOD THEREFOR
Simplified Explanation
The abstract describes a patent application for a three-dimensional flash memory with techniques to overcome interference and improve performance and manufacturing process.
- Techniques to suppress interference caused by an inter-cell insulation layer in a vertical cell and to form a stable vertical channel layer.
- Technique to reduce the length of wire compared to conventional three-dimensional flash memory, addressing issues of deterioration of chip characteristics such as operation speed and power consumption, and difficulty of wiring technique in the manufacturing process.
- Technique to improve horizontal density of channel layers and ONO (oxide-nitride-oxide) layers.
Potential Applications
This technology can be applied in various electronic devices that require high-density and high-performance memory storage, such as:
- Smartphones and tablets
- Solid-state drives (SSDs)
- Digital cameras
- Gaming consoles
Problems Solved
The patent application addresses several problems associated with three-dimensional flash memory:
- Interference caused by the inter-cell insulation layer in a vertical cell is suppressed, ensuring reliable operation.
- Chip characteristics such as operation speed and power consumption are improved, overcoming the deterioration observed in conventional three-dimensional flash memory.
- The difficulty of wiring technique in the manufacturing process is reduced, making it easier to produce the memory chips.
Benefits
The innovation described in the patent application offers several benefits:
- Improved performance: The techniques employed result in a stable vertical channel layer, reducing interference and improving the overall performance of the flash memory.
- Reduced wire length: By reducing the length of wire compared to conventional three-dimensional flash memory, the chip characteristics are improved, leading to enhanced operation speed and reduced power consumption.
- Higher density: The techniques used in this innovation allow for improved horizontal density of channel layers and ONO layers, enabling higher storage capacity in the same physical space.
Original Abstract Submitted
A three-dimensional flash memory is provided, and technique to suppress interference caused by an inter-cell insulation layer in a vertical cell and to form a stable vertical channel layer, a technique to reduce a length of wire than a conventional three-dimensional flash memory for overcoming problems of deterioration of chip characteristics such as operation speed and power consumption and difficulty of wiring technique in the manufacturing process, and a technique to improve horizontal density of channel layers and ONO layers are proposed.
