18153700. GATE PROFILE TUNING FOR MULTIGATE DEVICE simplified abstract (Taiwan Semiconductor Manufacturing Co., Ltd.)

GATE PROFILE TUNING FOR MULTIGATE DEVICE

Organization Name

Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor(s)

Cheng-I Lin of Hsinchu (TW)

Hao-Ming Tang of Taipei City (TW)

Shu-Han Chen of Hsinchu City (TW)

Chi On Chui of Hsinchu City (TW)

GATE PROFILE TUNING FOR MULTIGATE DEVICE - A simplified explanation of the abstract

This abstract first appeared for US patent application 18153700 titled 'GATE PROFILE TUNING FOR MULTIGATE DEVICE

Simplified Explanation

The patent application describes a method for tuning the gate profile in a gate structure used in semiconductor devices. The method involves the formation of a gate structure with a dummy gate and gate spacers on the sidewalls of the dummy gate. The dummy gate is partially removed to create a gate opening, and the gate profile is modified by treating and removing portions of the gate spacers. The remaining dummy gate is then removed to expose the channel layer, and a gate stack with a funnel-shaped profile is formed in the gate opening.

• The method involves forming a gate structure with a dummy gate and gate spacers.
• The dummy gate is partially removed to create a gate opening.
• The gate profile is modified by treating and removing portions of the gate spacers.
• The remaining dummy gate is removed to expose the channel layer.
• A gate stack with a funnel-shaped profile is formed in the gate opening.

Potential applications of this technology:

• This gate profile tuning method can be applied in the fabrication of semiconductor devices, such as transistors.
• It can improve the performance and efficiency of these devices by optimizing the gate profile.

Problems solved by this technology:

• Gate profile tuning is crucial for optimizing the performance of semiconductor devices.
• This method provides a precise and controlled way to modify the gate profile, allowing for better device performance.

Benefits of this technology:

• The gate profile tuning method allows for the creation of a gate stack with a funnel-shaped profile, which can enhance device performance.
• It provides a reliable and repeatable process for gate profile modification.
• The method can be easily integrated into existing semiconductor fabrication processes.

Original Abstract Submitted

Gate profile tuning techniques are disclosed herein. An exemplary gate profile tuning method includes forming a gate structure over a channel layer. The gate structure includes a dummy gate and gate spacers disposed along sidewalls of the dummy gate. The method further includes partially removing the dummy gate to form a gate opening that defines a gate profile. The gate profile is then modified by treating portions of the gate spacers (for example, by oxygen plasma treatment) and removing the treated portions of the gate spacers (for example, by oxide removal). After removing a remainder of the dummy gate to expose the channel layer, a gate stack of the gate structure is formed in the gate opening. The gate stack has a funnel-shaped profile. In some embodiments, a width of the gate stack above the channel layer is greater than a width of the gate stack below the channel layer.