18152153. CHIP STRUCTURE AND METHOD OF FABRICATING THE SAME simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)
CHIP STRUCTURE AND METHOD OF FABRICATING THE SAME
Organization Name
Taiwan Semiconductor Manufacturing Company, Ltd.
Inventor(s)
Kuo-Chiang Ting of Hsinchu City (TW)
Sung-Feng Yeh of Taipei City (TW)
CHIP STRUCTURE AND METHOD OF FABRICATING THE SAME - A simplified explanation of the abstract
This abstract first appeared for US patent application 18152153 titled 'CHIP STRUCTURE AND METHOD OF FABRICATING THE SAME
Simplified Explanation
The chip structure described in the abstract includes a bridge structure with an interconnect bridge, a dielectric layer surrounding the bridge, and through dielectric vias extending from the top to the bottom of the dielectric layer. Semiconductor dies are placed on the bridge structure, overlapping both the interconnect bridge and the dielectric layer, and are electrically connected to the interconnect bridge and at least one of the through dielectric vias. A die support holds the semiconductor dies between itself and the bridge structure, with its sidewall being coplanar with the sidewall of the bridge structure.
- Bridge structure with interconnect bridge and dielectric layer
- Semiconductor dies placed on the bridge structure
- Through dielectric vias connecting the top and bottom of the dielectric layer
- Die support holding the semiconductor dies
- Coplanar sidewalls of the die support and bridge structure
Potential Applications
- Advanced integrated circuits
- High-density electronic devices
- Microprocessors and memory chips
Problems Solved
- Improved electrical connections in chip structures
- Enhanced performance and reliability of semiconductor devices
- Increased efficiency in data processing and communication
Benefits
- Higher integration density
- Enhanced electrical connectivity
- Improved signal transmission speed
- Increased overall performance of electronic devices
Original Abstract Submitted
A chip structure provided herein includes a bridge structure including an interconnect bridge, a dielectric layer laterally surrounding the interconnect bridge and through dielectric vias extending from a top of the dielectric layer to a bottom of the dielectric layer, wherein a thickness of the interconnect bridge is identical to a height of each of the through dielectric vias; semiconductor dies disposed on the bridge structure, wherein each of the semiconductor dies overlaps both the interconnect bridge and the dielectric layer and is electrically connected to the interconnect bridge and at least one of the through dielectric vias; and a die support, the semiconductor dies being disposed between the die support and the bridge structure, wherein a sidewall of the die support is coplanar with a sidewall of the bridge structure.
