18151689. MEMS Structure with Reduced Peeling and Methods Forming the Same simplified abstract (Taiwan Semiconductor Manufacturing Co., Ltd.)
Contents
MEMS Structure with Reduced Peeling and Methods Forming the Same
Organization Name
Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor(s)
Pei-Wei Lee of Kaohsiung City (TW)
Szu-Hsien Lee of Tainan City (TW)
Yun-Chung Wu of Taipei City (TW)
Ming-Da Cheng of Taoyuan City (TW)
Ming -Ji Lii of Sinpu Township (TW)
MEMS Structure with Reduced Peeling and Methods Forming the Same - A simplified explanation of the abstract
This abstract first appeared for US patent application 18151689 titled 'MEMS Structure with Reduced Peeling and Methods Forming the Same
Simplified Explanation
The abstract describes a method for forming an interconnect structure over a semiconductor substrate. The interconnect structure consists of multiple dielectric layers and is located on a wafer. Metal pads are formed over the interconnect structure, and through-holes are created to penetrate through the wafer. These through-holes have top portions that go through the interconnect structure and middle portions that connect to and underlie the top portions. The middle portions are wider than the top portions. A metal layer is then formed to electrically connect to the metal pads, extending into the top portions of the through-holes.
- The method involves forming an interconnect structure over a semiconductor substrate.
- The interconnect structure includes multiple dielectric layers.
- Metal pads are formed over the interconnect structure.
- Through-holes are created to penetrate through the wafer.
- The through-holes have top portions that go through the interconnect structure.
- Middle portions of the through-holes connect to and underlie the top portions.
- The middle portions are wider than the top portions.
- A metal layer is formed to electrically connect to the metal pads.
- The metal layer extends into the top portions of the through-holes.
Potential applications of this technology:
- Integrated circuits and semiconductor devices
- Electronics manufacturing and assembly
Problems solved by this technology:
- Improved electrical connectivity and signal transmission in semiconductor devices
- Enhanced integration and miniaturization of electronic components
Benefits of this technology:
- Increased performance and reliability of integrated circuits
- Higher density and efficiency in electronic devices
- Improved manufacturing yield and cost-effectiveness
Original Abstract Submitted
A method includes forming an interconnect structure over a semiconductor substrate. The interconnect structure includes a plurality of dielectric layers, and the interconnect structure and the semiconductor substrate are in a wafer. A plurality of metal pads are formed over the interconnect structure. A plurality of through-holes are formed to penetrate through the wafer. The plurality of through-holes include top portions penetrating through the interconnect structure, and middle portions underlying and joining to the top portions. The middle portions are wider than respective ones of the top portions. A metal layer is formed to electrically connect to the plurality of metal pads. The metal layer extends into the top portions of the plurality of through-holes.
