18151663. Adding Sealing Material to Wafer edge for Wafer Bonding simplified abstract (Taiwan Semiconductor Manufacturing Co., Ltd.)

Adding Sealing Material to Wafer edge for Wafer Bonding

Organization Name

Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor(s)

Yu-Yi Huang of Taipei City (TW)

Yu-Hung Lin of Taichung City (TW)

Wei-Ming Wang of Taichung City (TW)

Chen Chen of New Taipei City (TW)

Shih-Peng Tai of Xinpu Township (TW)

Kuo-Chung Yee of Taoyuan City (TW)

Adding Sealing Material to Wafer edge for Wafer Bonding - A simplified explanation of the abstract

This abstract first appeared for US patent application 18151663 titled 'Adding Sealing Material to Wafer edge for Wafer Bonding

Simplified Explanation

The method described in the patent application involves forming a sealing layer at the edge region of a wafer, bonding it to another wafer to create a wafer stack, and then performing an edge trimming process on the stack. The process leaves a portion of the sealing layer intact and forms an interconnect structure in the second wafer, which includes redistribution lines connected to integrated circuit devices.

• Formation of a sealing layer at the edge region of a wafer
• Bonding of the wafer to another wafer to create a wafer stack
• Edge trimming process on the wafer stack
• Formation of an interconnect structure in the second wafer

Potential Applications

This technology could be applied in the semiconductor industry for the manufacturing of advanced integrated circuits and microelectronics.

Problems Solved

This technology solves the problem of efficiently forming interconnect structures in wafer stacks while maintaining the integrity of the sealing layer.

Benefits

The benefits of this technology include improved reliability and performance of integrated circuits, as well as cost savings in the manufacturing process.

Potential Commercial Applications

One potential commercial application of this technology could be in the production of high-performance microprocessors for consumer electronics.

Possible Prior Art

One possible prior art for this technology could be the use of edge trimming processes in semiconductor manufacturing to improve the quality of integrated circuits.

How does this technology compare to existing methods for forming interconnect structures in wafer stacks?

This article does not provide a direct comparison with existing methods for forming interconnect structures in wafer stacks.

What are the specific materials and techniques used in the edge trimming process described in the patent application?

The article does not detail the specific materials and techniques used in the edge trimming process.

Original Abstract Submitted

A method includes forming a first sealing layer at a first edge region of a first wafer; and bonding the first wafer to a second wafer to form a wafer stack. At a time after the bonding, the first sealing layer is between the first edge region of the first wafer and a second edge region of the second wafer, with the first edge region and the second edge region comprising bevels. An edge trimming process is then performed on the wafer stack. After the edge trimming process, the second edge region of the second wafer is at least partially removed, and a portion of the first sealing layer is left as a part of the wafer stack. An interconnect structure is formed as a part of the second wafer. The interconnect structure includes redistribution lines electrically connected to integrated circuit devices in the second wafer.