18151483. MEMORY ARRAY AND OPERATION METHOD THEREOF simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)

MEMORY ARRAY AND OPERATION METHOD THEREOF

Organization Name

Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor(s)

Wen-Ling Lu of Taoyuan City (TW)

Chen-Jun Wu of Hsinchu (TW)

Ya-Yun Cheng of Taichung City (TW)

Sheng-Chih Lai of Hsinchu County (TW)

Yi-Ching Liu of Hsinchu City (TW)

Yu-Ming Lin of Hsinchu City (TW)

Feng-Cheng Yang of Hsinchu County (TW)

Chung-Te Lin of Tainan City (TW)

MEMORY ARRAY AND OPERATION METHOD THEREOF - A simplified explanation of the abstract

This abstract first appeared for US patent application 18151483 titled 'MEMORY ARRAY AND OPERATION METHOD THEREOF

Simplified Explanation

The memory array described in the patent application includes first and second ferroelectric memory devices with a common source/drain electrode and two respective source/drain electrodes. These devices are formed along a gate electrode, a channel layer, and a ferroelectric layer.

• Common source/drain electrode and two respective source/drain electrodes
• First and second auxiliary gates capacitively coupled to the channel layer
• Configuration of the first and second auxiliary gates between the common source/drain electrode and the respective source/drain electrodes

• • Potential Applications:**

- Non-volatile memory storage - Low-power consumption electronic devices - High-speed data processing applications

• • Problems Solved:**

- Reduced power consumption compared to traditional memory devices - Improved data retention and reliability - Enhanced performance in high-speed applications

• • Benefits:**

- Increased efficiency in data storage and processing - Longer lifespan of electronic devices - Improved overall performance and reliability

Original Abstract Submitted

A memory array and an operation method of the memory array are provided. The memory array includes first and second ferroelectric memory devices formed along a gate electrode, a channel layer and a ferroelectric layer between the gate electrode and the channel layer. The ferroelectric memory devices include: a common source/drain electrode and two respective source/drain electrodes, separately in contact with a side of the channel layer opposite to the ferroelectric layer, wherein the common source/drain electrode is disposed between the respective source/drain electrodes; and first and second auxiliary gates, capacitively coupled to the channel layer, wherein the first auxiliary gate is located between the common source/drain electrode and one of the respective source/drain electrodes, and the second auxiliary gate is located between the common source/drain electrode and the other respective source/drain electrode.