18151279. Dielectric Walls for Complementary Field Effect Transistors simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)

Dielectric Walls for Complementary Field Effect Transistors

Organization Name

Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor(s)

Cheng-Ting Chung of Hsinchu City (TW)

Yi-Bo Liao of Hsinchu (TW)

Jin Cai of Hsinchu City (TW)

Dielectric Walls for Complementary Field Effect Transistors - A simplified explanation of the abstract

This abstract first appeared for US patent application 18151279 titled 'Dielectric Walls for Complementary Field Effect Transistors

Simplified Explanation

The patent application describes a device with nanostructures abutting a dielectric wall, lower and upper source/drain regions adjacent to different subsets of the nanostructures, and a shared source/drain contact extending into the dielectric wall.

• Nanostructures abut a dielectric wall
• Lower and upper source/drain regions are connected to different subsets of nanostructures
• Upper source/drain region is oppositely doped from the lower source/drain region
• Shared source/drain contact extends into the dielectric wall

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1. 1. 1. Potential Applications

• Advanced semiconductor devices
• High-performance transistors
• Nanoelectronics

1. 1. 1. Problems Solved

• Improved performance and efficiency of semiconductor devices
• Enhanced control over charge carriers in transistors
• Reduction of leakage currents

1. 1. 1. Benefits

• Increased speed and reliability of electronic devices
• Lower power consumption
• Miniaturization of electronic components

Original Abstract Submitted

In an embodiment, a device includes: a dielectric wall; nanostructures abutting the dielectric wall; a lower source/drain region adjoining a lower subset of the nanostructures; an upper source/drain region adjoining an upper subset of the nanostructures, the upper source/drain region oppositely doped from the lower source/drain region; and a shared source/drain contact contacting the upper source/drain region and the lower source/drain region, the shared source/drain contact extending into the dielectric wall.