18150810. COMPUTATION METHOD AND COMPUTATION APPARATUS WITH INPUT SWAPPING simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)
COMPUTATION METHOD AND COMPUTATION APPARATUS WITH INPUT SWAPPING
Organization Name
Taiwan Semiconductor Manufacturing Company, Ltd.
Inventor(s)
Win-San Khwa of Taipei City (TW)
Yi-Lun Lu of New Taipei City (TW)
Meng-Fan Chang of Taichung City (TW)
COMPUTATION METHOD AND COMPUTATION APPARATUS WITH INPUT SWAPPING - A simplified explanation of the abstract
This abstract first appeared for US patent application 18150810 titled 'COMPUTATION METHOD AND COMPUTATION APPARATUS WITH INPUT SWAPPING
Simplified Explanation
The patent application describes a computation apparatus and method with input swapping, which includes a non-zero detection circuit, a swapper policy circuit, a swapper matrix circuit, and an adder tree.
- Non-zero detection circuit inspects non-zero operands in input vectors and generates a non-zero indicative signal.
- Swapper policy circuit interprets the non-zero indicative signal and generates MUX selection signals for swapping non-zero operands based on swapping policies.
- Swapper matrix circuit performs swapping on operands in input vectors according to the MUX selection signal.
- Adder tree receives input vectors with swapped operands and performs additions to output a computation result.
Potential Applications
- High-performance computing
- Signal processing
- Cryptography
Problems Solved
- Efficient handling of non-zero operands in computation
- Optimized computation process
- Improved accuracy in computation results
Benefits
- Faster computation speed
- Enhanced accuracy
- Increased efficiency in processing non-zero operands
Original Abstract Submitted
A computation apparatus and a computation method with input swapping are provided. The computation apparatus includes a non-zero detection circuit, a swapper policy circuit, a swapper matrix circuit, and an adder tree. The non-zero detection circuit is configured to receive input vectors, inspect non-zero operands in the input vectors and generate a non-zero indicative signal indicating the non-zero operands. The swapper policy circuit is configured to receive and interpret the non-zero indicative signal, and generate multiplexer (MUX) selection signals for swapping the non-zero operands according to a set of swapping policies. The swapper matrix circuit is configured to receive the input vectors and the MUX selection signal, and perform swapping on operands in the input vectors according to the MUX selection signal. The adder tree is configured to receive the input vectors with the swapped operands and perform additions on the input vectors to output a computation result.
