18150289. FERROELECTRIC MEMORY DEVICE WITH BLOCKING LAYER simplified abstract (Taiwan Semiconductor Manufacturing Co., Ltd.)

From WikiPatents
Jump to navigation Jump to search

FERROELECTRIC MEMORY DEVICE WITH BLOCKING LAYER

Organization Name

Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor(s)

Tzu-Yu Chen of Kaohsiung City (TW)

Chu-Jie Huang of Tainan City (TW)

Wan-Chen Chen of Hsinchu City (TW)

Fu-Chen Chang of New Taipei City (TW)

Sheng-Hung Shih of Hsinchu City (TW)

Kuo-Chi Tu of Hsin-Chu (TW)

FERROELECTRIC MEMORY DEVICE WITH BLOCKING LAYER - A simplified explanation of the abstract

This abstract first appeared for US patent application 18150289 titled 'FERROELECTRIC MEMORY DEVICE WITH BLOCKING LAYER

Simplified Explanation

The present patent application is about a memory cell that includes a blocking layer designed to prevent the diffusion of metal from one electrode to a ferroelectric layer in the memory cell. The blocking layer is positioned between the ferroelectric layer and one of the top and bottom electrodes, both of which are made of metal.

  • The memory cell has a blocking layer that stops metal diffusion from an electrode to a ferroelectric layer.
  • The blocking layer is located between the ferroelectric layer and one of the top and bottom electrodes.
  • Both the top and bottom electrodes are made of metal.
  • The metal of one of the electrodes has the lowest electronegativity among the metals used for the electrodes, making it the most reactive and likely to diffuse.

Potential Applications:

  • Memory cells with improved stability and reliability.
  • Non-volatile memory devices.
  • Ferroelectric random-access memory (FeRAM) technology.

Problems Solved:

  • Preventing metal diffusion in memory cells.
  • Enhancing the stability and reliability of memory cells.
  • Reducing the risk of electrode degradation.

Benefits:

  • Improved performance and longevity of memory cells.
  • Enhanced data retention and reliability.
  • Lower risk of electrode degradation and failure.


Original Abstract Submitted

Various embodiments of the present disclosure are directed towards a memory cell comprising a blocking layer configured to block diffusion of metal from an electrode of the memory cell to a ferroelectric layer of the memory cell. More particularly, the blocking layer and the ferroelectric layer are between a top electrode of the memory cell and a bottom electrode of the memory cell, which both comprise metal. Further, the blocking layer is between the ferroelectric layer and the electrode, which corresponds to one of the top and bottom electrodes. In some embodiments, the metal of the one of the top and bottom electrodes has a lowest electronegativity amongst the metals of top and bottom electrodes and is hence the most reactive and likely to diffuse amongst the metals of top and bottom electrodes.

Retrieved from "http://wikipatents.org/index.php?title=18150289._FERROELECTRIC_MEMORY_DEVICE_WITH_BLOCKING_LAYER_simplified_abstract_(Taiwan_Semiconductor_Manufacturing_Co.,_Ltd.)&oldid=31708"