18149734. VERTICALLY STACKED FeFETS WITH COMMON CHANNEL simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)
Contents
- 1 VERTICALLY STACKED FeFETS WITH COMMON CHANNEL
- 1.1 Organization Name
- 1.2 Inventor(s)
- 1.3 VERTICALLY STACKED FeFETS WITH COMMON CHANNEL - A simplified explanation of the abstract
- 1.4 Simplified Explanation
- 1.5 Potential Applications
- 1.6 Problems Solved
- 1.7 Benefits
- 1.8 Potential Commercial Applications
- 1.9 Possible Prior Art
- 1.10 Unanswered Questions
- 1.11 Original Abstract Submitted
VERTICALLY STACKED FeFETS WITH COMMON CHANNEL
Organization Name
Taiwan Semiconductor Manufacturing Company, Ltd.
Inventor(s)
Georgios Vellianitis of Heverlee (BE)
Gerben Doornbos of Kessel-Lo (BE)
VERTICALLY STACKED FeFETS WITH COMMON CHANNEL - A simplified explanation of the abstract
This abstract first appeared for US patent application 18149734 titled 'VERTICALLY STACKED FeFETS WITH COMMON CHANNEL
Simplified Explanation
The abstract describes a patent application for a three-dimensional structure of Ferroelectric Field Effect Transistors (FeFETs) with high area density and additional design flexibility.
- FeFETs are structured in vertical columns with source/drain electrodes provided by horizontal conductive layers interleaved with dielectric layers.
- Channels for FeFETs are created by continuous semiconductor layers in each vertical column.
- Gate electrodes are formed by a control gate structure connecting the gate electrodes in parallel.
- Source/drain electrodes of multiple vertical columns and tiers can be connected in parallel, increasing design flexibility.
- This structure allows for high area density, an extra degree of freedom in circuit design, and the use of oxide semiconductor channels.
Potential Applications
The technology can be applied in high-density integrated circuits, memory devices, and low-power electronics.
Problems Solved
This innovation solves the problem of limited area density and design flexibility in traditional FeFET structures.
Benefits
The benefits of this technology include increased area density, enhanced design flexibility, and the use of oxide semiconductor channels.
Potential Commercial Applications
The technology can be utilized in the development of advanced semiconductor devices, memory chips, and energy-efficient electronics.
Possible Prior Art
One possible prior art could be the use of traditional FeFET structures with lower area density and design flexibility.
Unanswered Questions
How does this technology compare to existing FeFET structures in terms of performance and power consumption?
The article does not provide a direct comparison between this three-dimensional FeFET structure and existing FeFET structures in terms of performance and power consumption.
What are the potential challenges in scaling up this technology for mass production?
The article does not address the potential challenges in scaling up this three-dimensional FeFET structure for mass production, such as manufacturing complexity or cost implications.
Original Abstract Submitted
Ferroelectric field effect transistors are in a three-dimensional structure that includes vertical columns. Source/drain electrodes are provided by horizontal conductive layers that are interleaved with dielectric layers. Channels for the FeFETs in each vertical column are provided by a continuous semiconductor layer, e.g., a vertical strip of semiconductor. Another vertical strip may provide the ferroelectric layers for the FeFETs in the vertical column. The gate electrodes are provided by a control gate structure that connects the gate electrodes in parallel. The source/drain electrodes of multiple vertical columns may be connected in parallel. The source/drain electrodes of multiple tiers may also be connected in parallel. This structure provides high area density, adds an extra degree of freedom in circuit design, and lends itself to the use of oxide semiconductor channels.
