18149671. SEMICONDUCTOR STRUCTURE AND METHOD FOR FABRICATING THE SAME simplified abstract (Changxin Memory Technologies, Inc.)
Contents
SEMICONDUCTOR STRUCTURE AND METHOD FOR FABRICATING THE SAME
Organization Name
Changxin Memory Technologies, Inc.
Inventor(s)
SEMICONDUCTOR STRUCTURE AND METHOD FOR FABRICATING THE SAME - A simplified explanation of the abstract
This abstract first appeared for US patent application 18149671 titled 'SEMICONDUCTOR STRUCTURE AND METHOD FOR FABRICATING THE SAME
Simplified Explanation
The patent application describes a semiconductor structure and a method for fabricating it. Here are the key points:
- The method involves providing a substrate and forming active pillars and isolation layers in the substrate.
- Word line trenches are then formed in the active pillars and isolation layers, extending along a first direction.
- A first word line and a second word line are formed in the word line trenches.
- The first word line and the second word line, together with the active pillar, form first and second gate channels respectively.
- The width of the first gate channel and the width of the second gate channel, along the first direction, are greater than the perimeter of the active pillar.
Potential applications of this technology:
- This semiconductor structure and fabrication method can be used in various electronic devices, such as integrated circuits and memory devices.
- It can improve the performance and efficiency of these devices by optimizing the gate channel width and the active pillar design.
Problems solved by this technology:
- The technology addresses the challenge of optimizing the gate channel width in a semiconductor structure.
- It provides a solution for improving the performance and efficiency of electronic devices by maximizing the gate channel width relative to the active pillar perimeter.
Benefits of this technology:
- The optimized gate channel width allows for better control of the flow of electrical current in the semiconductor structure.
- This can result in improved device performance, reduced power consumption, and enhanced overall efficiency.
- The fabrication method described in the patent application provides a practical and efficient way to achieve this optimized gate channel width.
Original Abstract Submitted
Embodiments provide a semiconductor structure and a method for fabricating the same. The method includes: providing a substrate; forming, in the substrate, active pillars spaced and isolation layers configured to isolate the active pillars; forming, in an active pillars and an isolation layers, word line trenches extending along a first direction; and forming a first word line in the first word line trench and a second word line in the second word line trench, where opposite surfaces of the first word line form a first gate channel together with the active pillar, opposite surfaces of the second word line form a second gate channel together with the active pillar, and sum of a width of the first gate channel along the first direction and a width of the second gate channel along the first direction is greater than a perimeter of the active pillar.
