18149302. MEMORY DEVICE FOR COLUMN REPAIR simplified abstract (SAMSUNG ELECTRONICS CO., LTD.)
Contents
MEMORY DEVICE FOR COLUMN REPAIR
Organization Name
Inventor(s)
Jooyong Park of Hwaseong-si (KR)
Daeseok Byeon of Seongnam-si (KR)
MEMORY DEVICE FOR COLUMN REPAIR - A simplified explanation of the abstract
This abstract first appeared for US patent application 18149302 titled 'MEMORY DEVICE FOR COLUMN REPAIR
Simplified Explanation
The memory device described in the patent application includes a memory cell array with normal memory cells and redundant memory cells. It also includes first page buffers connected to the normal memory cells through first bit lines and second page buffers connected to the redundant memory cells through second bit lines.
- The memory device has normal memory cells and redundant memory cells.
- First page buffers are connected to the normal memory cells through first bit lines.
- Second page buffers are connected to the redundant memory cells through second bit lines.
- The first and second bit lines are arranged in different areas in a line in a first direction.
- If a normal memory cell connected to the first bit line group is determined as defective, it is replaced with a redundant memory cell connected to the third bit line group.
Potential applications of this technology:
- Memory devices in electronic devices such as smartphones, tablets, and computers.
- Storage devices in data centers and servers.
- Embedded memory in various electronic systems.
Problems solved by this technology:
- Efficient replacement of defective memory cells.
- Improved reliability and performance of memory devices.
- Reducing the impact of defective memory cells on overall memory capacity.
Benefits of this technology:
- Increased yield and reduced cost in memory manufacturing.
- Enhanced data integrity and error correction capabilities.
- Improved overall memory performance and reliability.
Original Abstract Submitted
A memory device includes a memory cell array including normal memory cells and redundant memory cells; first page buffers connected to the normal memory cells through first bit lines including a first bit line group and a second bit line group and arranged in a first area corresponding to the first bit lines in a line in a first direction; and second page buffers connected to the redundant memory cells through second bit lines including a third bit line group and a fourth bit line group and arranged in a second area corresponding to the second bit lines in a line in the first direction, wherein, when at least one normal memory cell connected to the first bit line group is determined as a defective cell, normal memory cells connected to the first bit line group are replaced with redundant memory cells connected to the third bit line group.
