18149284. EXTENDED VIA CONNECT FOR PIXEL ARRAY simplified abstract (Taiwan Semiconductor Manufacturing Co., Ltd.)

EXTENDED VIA CONNECT FOR PIXEL ARRAY

Organization Name

Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor(s)

Meng-Hsien Lin of Tainan City (TW)

Hsing-Chih Lin of Tainan City (TW)

Ming-Tsong Wang of Taipei City (TW)

Min-Feng Kao of Chiayi City (TW)

Kuan-Hua Lin of New Taipei City (TW)

Jen-Cheng Liu of Hsin-Chu City (TW)

Dun-Nian Yaung of Taipei City (TW)

Ko Chun Liu of Toufen Township (TW)

EXTENDED VIA CONNECT FOR PIXEL ARRAY - A simplified explanation of the abstract

This abstract first appeared for US patent application 18149284 titled 'EXTENDED VIA CONNECT FOR PIXEL ARRAY

Simplified Explanation

Some embodiments of the present disclosure relate to an integrated chip with an extended via that has a smaller footprint than a wire, allowing for reduced spacing and size of pixels in capacitor arrays for pixel circuits.

• Integrated chip includes extended via with smaller footprint than wire
• Extended via replaces wire and adjoining via in locations with limited sizing and spacing
• Allows for reduced pixel size and spacing in capacitor arrays for pixel circuits

Potential Applications

The technology could be applied in the manufacturing of high-resolution displays, image sensors, and other electronic devices where reducing pixel size and spacing is crucial.

Problems Solved

The technology solves the problem of limited sizing and spacing in integrated chips, allowing for the creation of smaller pixels and more compact designs in capacitor arrays for pixel circuits.

Benefits

The benefits of this technology include increased pixel density, improved resolution, and enhanced performance in electronic devices that require high pixel counts and compact designs.

Potential Commercial Applications

• "Enhancing Pixel Density in Integrated Chips for High-Resolution Displays"

Possible Prior Art

One possible prior art could be the use of traditional wires and vias in integrated chips, which may not offer the same level of compactness and efficiency as the extended via technology described in this patent application.

How does the extended via technology impact the overall cost of manufacturing integrated chips?

The cost implications of implementing the extended via technology in integrated chips are not addressed in the abstract. It would be interesting to know if the smaller footprint of the extended via leads to cost savings in the manufacturing process.

What are the potential challenges or limitations of using extended vias in integrated chips?

The abstract does not mention any potential drawbacks or challenges associated with the use of extended vias. It would be important to understand if there are any limitations to this technology, such as reliability issues or compatibility with existing manufacturing processes.

Original Abstract Submitted

Some embodiments of the present disclosure relate to an integrated chip including an extended via that spans a combined height of a wire and a via and that has a smaller footprint than the wire. The extended via may replace a wire and an adjoining via at locations where the sizing and the spacing of the wire are reaching lower limits. Because the extended via has a smaller footprint than the wire, replacing the wire and the adjoining via with the extended via relaxes spacing and allows the size of the pixel to be further reduced. The extended via finds application for capacitor arrays used for pixel circuits.