18149240. DEEP TRENCH ISOLATION STRUCTURE FOR HIGH RESOLUTION CIS PIXEL simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)

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DEEP TRENCH ISOLATION STRUCTURE FOR HIGH RESOLUTION CIS PIXEL

Organization Name

Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor(s)

Chih Cheng Shih of Kaohsiung City (TW)

Tsun-Kai Tsao of Tainan City (TW)

Jiech-Fun Lu of Madou Township (TW)

Hung-Wen Hsu of Tainan City (TW)

Bing Cheng You of Taichung City (TW)

Wen-Chang Kuo of Tainan City (TW)

DEEP TRENCH ISOLATION STRUCTURE FOR HIGH RESOLUTION CIS PIXEL - A simplified explanation of the abstract

This abstract first appeared for US patent application 18149240 titled 'DEEP TRENCH ISOLATION STRUCTURE FOR HIGH RESOLUTION CIS PIXEL

Simplified Explanation

The abstract describes a patent application for a process to form trenches for back side isolation structures in CMOS image sensors. The process involves cyclic steps of etching to add depth segments to the trenches and coating the segments with an etch-resistant material to limit lateral etching and substrate damage.

  • Each cycle of the process includes etching to add a depth segment to the trenches.
  • The depth segment is coated with an etch-resistant material to limit lateral etching and substrate damage.
  • The resulting trenches have vertically spaced nodes.
  • The process may result in a 10% increase in photodiode area and a 30-40% increase in full well capacity.

Potential Applications

The technology can be applied in the manufacturing of CMOS image sensors for various electronic devices such as smartphones, digital cameras, and surveillance systems.

Problems Solved

1. Limiting lateral etching and substrate damage during trench formation. 2. Increasing photodiode area and full well capacity in CMOS image sensors.

Benefits

1. Improved performance and image quality in CMOS image sensors. 2. Enhanced sensitivity and dynamic range in capturing images. 3. Cost-effective manufacturing process for back side isolation structures.


Original Abstract Submitted

Trenches in which to form a back side isolation structure for an array of CMOS image sensors are formed by a cyclic process that allows the trenches to be kept narrow. Each cycle of the process includes etching to add a depth segment to the trenches and coating the depth segment with an etch-resistant coating. The following etch step will break through the etch-resistant coating at the bottom of the trench but the etch-resistant coating will remain in the upper part of the trench to limit lateral etching and substrate damage. The resulting trenches have a series of vertically spaced nodes. The process may result in a 10% increase in photodiode area and a 30-40% increase in full well capacity.

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