18146591. WIRE BONDS FOR GALVANIC ISOLATION DEVICE simplified abstract (TEXAS INSTRUMENTS INCORPORATED)

WIRE BONDS FOR GALVANIC ISOLATION DEVICE

Organization Name

TEXAS INSTRUMENTS INCORPORATED

Inventor(s)

Jeffrey Alan West of Dallas TX (US)

Hung-Yu Chou of Taipei city (TW)

Byron Lovell Williams of Plano TX (US)

Thomas Dyer Bonifield of Dallas TX (US)

WIRE BONDS FOR GALVANIC ISOLATION DEVICE - A simplified explanation of the abstract

This abstract first appeared for US patent application 18146591 titled 'WIRE BONDS FOR GALVANIC ISOLATION DEVICE

Simplified Explanation

The microelectronic device described in the patent application includes a galvanic isolation component with upper and lower isolation elements, dielectric plateau, and upper and lower bond pads. High voltage wire bonds are placed on the upper bond pads, while low voltage wire bonds are placed on the lower bond pads.

• The microelectronic device features a galvanic isolation component with upper and lower isolation elements.
• High voltage wire bonds are placed on the upper bond pads, extending vertically for a distance greater than the lateral isolation distance.
• Low voltage wire bonds are placed on the lower bond pads, with a loop height directly over the substrate perimeter.

Potential Applications

The technology described in the patent application could be used in:

• Power electronics
• Electric vehicles
• Renewable energy systems

Problems Solved

This technology helps to:

• Improve galvanic isolation in microelectronic devices
• Enhance the performance of high voltage wire bonds
• Optimize the layout of bond pads in microelectronic devices

Benefits

The benefits of this technology include:

• Increased safety in high voltage applications
• Enhanced reliability of microelectronic devices
• Improved performance of wire bonds

Potential Commercial Applications

The technology could be applied in various industries, including:

• Semiconductor manufacturing
• Automotive industry
• Power distribution sector

Possible Prior Art

One possible prior art for this technology could be the use of dielectric materials in microelectronic devices to provide isolation between different components.

How does this technology compare to existing galvanic isolation solutions in microelectronic devices?

This article does not provide a direct comparison with existing galvanic isolation solutions in microelectronic devices. Further research or a comparative analysis would be needed to answer this question.

What are the specific manufacturing processes involved in implementing this technology in microelectronic devices?

The article does not delve into the specific manufacturing processes involved in implementing this technology. Additional information or a detailed study of the manufacturing processes would be required to answer this question.

Original Abstract Submitted

A microelectronic device includes a galvanic isolation component having a lower isolation element over a substrate with lower bond pads connected to the lower isolation element, a dielectric plateau over the lower isolation element that does not extend to the lower bond pads, and an upper isolation element and upper bond pads over the dielectric plateau. The upper bond pads are laterally separated from the lower bond pads by an isolation distance. The microelectronic device includes high voltage wire bonds on the upper bond pads that extend upward, within 10 degrees of vertical, for a vertical distance greater than the isolation distance. The microelectronic device further includes low voltage wire bonds on the lower bond pads that have a loop height directly over a perimeter of the substrate that is less than 5 times a wire diameter of the low voltage wire bonds.