18143314. SEMICONDUCTOR MEMORY DEVICE simplified abstract (Samsung Electronics Co., Ltd.)
Contents
SEMICONDUCTOR MEMORY DEVICE
Organization Name
Inventor(s)
SEMICONDUCTOR MEMORY DEVICE - A simplified explanation of the abstract
This abstract first appeared for US patent application 18143314 titled 'SEMICONDUCTOR MEMORY DEVICE
Simplified Explanation
The semiconductor memory device described in the abstract includes a substrate with conductive lines extending in a first horizontal direction and spaced apart from each other in a second horizontal direction perpendicular to the first direction. The device also includes cell stacks with vertical transistor structures and connection contacts, as well as capacitor structures connected to the transistor structures.
- Plurality of conductive lines on substrate
- First cell stack with first vertical transistor structures and connection contacts
- Second cell stack on first cell stack with second vertical transistor structures and connection contacts
- Capacitor structures on second cell stack connected to vertical transistor structures
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- Potential Applications
- Data storage in electronic devices
- Memory modules in computers and servers
- Mobile devices such as smartphones and tablets
- Problems Solved
- Increased memory capacity in a compact space
- Efficient data storage and retrieval
- Improved performance and speed of memory devices
- Benefits
- Higher storage density
- Faster data access and transfer speeds
- Enhanced overall performance of electronic devices
Original Abstract Submitted
A semiconductor memory device including a substrate, a plurality of conductive lines extending in a first horizontal direction on the substrate and spaced apart from each other in a second horizontal direction perpendicular to the first horizontal direction, a first cell stack on each of the plurality of conductive lines and including a plurality of first vertical transistor structures and a plurality of first connection contacts, a second cell stack on the first cell stack and including a plurality of second vertical transistor structures and a plurality of second connection contacts, and a plurality of capacitor structures arranged on the second cell stack and connected to the plurality of first vertical transistor structures and the plurality of second vertical transistor structures.
