18141675. SEMICONDUCTOR CHIP AND SEMICONDUCTOR PACKAGE simplified abstract (SAMSUNG ELECTRONICS CO., LTD.)
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SEMICONDUCTOR CHIP AND SEMICONDUCTOR PACKAGE
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Inventor(s)
SEMICONDUCTOR CHIP AND SEMICONDUCTOR PACKAGE - A simplified explanation of the abstract
This abstract first appeared for US patent application 18141675 titled 'SEMICONDUCTOR CHIP AND SEMICONDUCTOR PACKAGE
Simplified Explanation
The semiconductor package described in the patent application consists of two semiconductor chips stacked on top of each other. The first chip has a substrate, pads, an insulating layer, and wiring patterns connected to the pads. The second chip is positioned below the first chip and has a substrate, pads, an insulating layer, and through-electrodes connected to the pads.
Key points about the patent/innovation:
- The semiconductor package includes two stacked chips with interconnecting wiring patterns.
- The first chip has pads on its front surface, surrounded by an insulating layer.
- The wiring patterns are located between the first chip and its pads, electrically connecting them.
- The second chip has pads on its substrate, which contact the pads of the first chip.
- The second chip also has an insulating layer surrounding its pads, which contacts the first insulating layer.
- Through-electrodes penetrate through the second chip's substrate and connect to its pads.
- The wiring patterns include top wiring patterns adjacent to the first pads in a perpendicular direction.
- The top wiring patterns have different occupied areas between adjacent first pads in different regions.
- The first group of pads has smaller areas compared to the second group of pads.
Potential applications of this technology:
- Semiconductor packaging for electronic devices such as smartphones, tablets, and computers.
- Integrated circuits and microprocessors that require stacked chip configurations.
- High-density electronic devices that benefit from compact and efficient chip stacking.
Problems solved by this technology:
- Enables efficient stacking of semiconductor chips, reducing the overall size of electronic devices.
- Provides electrical connectivity between stacked chips through wiring patterns and through-electrodes.
- Improves the performance and functionality of integrated circuits by allowing for more complex designs in a compact form factor.
Benefits of this technology:
- Compact and space-saving design, allowing for smaller and thinner electronic devices.
- Improved electrical connectivity between stacked chips, enhancing overall performance.
- Enables the integration of multiple functionalities within a single package, increasing versatility and efficiency.
Original Abstract Submitted
A semiconductor package includes a first semiconductor chip including a first substrate, a plurality of first pads disposed on a front surface of the first substrate, a first insulating layer surrounding the plurality of first pads, and a plurality of wiring patterns disposed between the first substrate and the plurality of first pads and electrically connected to the plurality of first pads; and a second semiconductor chip disposed below the first semiconductor chip and including a second substrate, a plurality of second pads disposed on the second substrate and contacting the plurality of first pads, a second insulating layer surrounding the plurality of second pads and contacting the first insulating layer, and a plurality of through-electrodes penetrating through the second substrate to be connected to the plurality of second pads. The plurality of wiring patterns include top wiring patterns adjacent to the plurality of first pads in a direction perpendicular to the front surface. On a plane parallel to the front surface, within a first region having a first shape and first region area from a top down view, first top wiring patterns have a first occupied area between adjacent first pads of a first group of first pads from among the plurality of first pads, and within a second region having the first shape and first region area from a top down view, second top wiring patterns have a second occupied area, larger than the first occupied area, between adjacent first pads of a second group of first pads from among the plurality of first pads. From a top down view, each pad of the first group of first pads has a first area, and each pad of the second group of first pads has a second area, wherein the first area is smaller than a second area.
