18140960. SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING SAME simplified abstract (SAMSUNG ELECTRONICS CO., LTD.)
SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING SAME
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SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING SAME - A simplified explanation of the abstract
This abstract first appeared for US patent application 18140960 titled 'SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING SAME
Simplified Explanation
The semiconductor package described in the patent application includes a first semiconductor chip and a second semiconductor chip stacked on top of the first chip. The first chip has a substrate with a bonding pad and a passivation layer exposing part of the bonding pad. The second chip has a substrate with an insulation layer, a bonding pad, an alignment key pattern, and a passivation layer covering part of the alignment key pattern and exposing part of the bonding pad. The bonding pads of the two chips are directly bonded, as are the passivation layers.
- The semiconductor package includes two stacked semiconductor chips with directly bonded bonding pads and passivation layers.
- The first chip has a bonding pad and passivation layer, while the second chip has an alignment key pattern in addition to these features.
- The alignment key pattern helps ensure proper alignment and connection between the two chips during bonding.
Potential Applications
- This technology can be used in various electronic devices such as smartphones, tablets, and computers.
- It can also be applied in automotive electronics, medical devices, and industrial equipment.
Problems Solved
- Ensures secure and reliable bonding between stacked semiconductor chips.
- Facilitates proper alignment during the bonding process, reducing the risk of misalignment and connection issues.
Benefits
- Improved performance and reliability of semiconductor packages.
- Enables the development of smaller and more compact electronic devices.
- Simplifies the manufacturing process of stacked semiconductor chips.
Original Abstract Submitted
A semiconductor package includes; a first semiconductor chip and a second semiconductor chip stacked on the first semiconductor chip. The first semiconductor chip includes; a first substrate, a first bonding pad on a first surface of the first substrate, and a first passivation layer on the first surface of the first substrate exposing at least a portion of the first bonding pad. The second semiconductor chip includes; a second substrate, a second insulation layer on a front surface of the second substrate, a second bonding pad on the second insulation layer, a first alignment key pattern on the second insulation layer, and a second passivation layer on the second insulation layer, covering at least a portion of the first alignment key pattern, and exposing at least a portion of the second bonding pad, wherein the first bonding pad and the second bonding pad are directly bonded, and the first passivation layer and the second passivation layer are directly bonded.
