18138363. SEMICONDUCTOR PACKAGE AND METHOD OF FABRICATING THE SAME simplified abstract (Samsung Electronics Co., Ltd.)

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SEMICONDUCTOR PACKAGE AND METHOD OF FABRICATING THE SAME

Organization Name

Samsung Electronics Co., Ltd.

Inventor(s)

Yong Hwan Kwon of Suwon-si (KR)

SEMICONDUCTOR PACKAGE AND METHOD OF FABRICATING THE SAME - A simplified explanation of the abstract

This abstract first appeared for US patent application 18138363 titled 'SEMICONDUCTOR PACKAGE AND METHOD OF FABRICATING THE SAME

Simplified Explanation

The semiconductor package described in the patent application includes a base substrate, an interposer package, and first and second semiconductor chips. The interposer package consists of a first redistribution structure with a first insulating layer, a second insulating layer on top of the first insulating layer, and first and second redistribution layers on the respective insulating layers. The interposer package also includes a bridge chip on the bottom surface of the first redistribution structure, a connection structure on the bottom surface of the first redistribution structure with multiple wiring layers connected to the semiconductor chips, and a bonding structure on a third insulating layer on the second insulating layer, bonding the semiconductor chips to the first redistribution structure. The second redistribution layer contains a contact plug within the third insulating layer.

  • The semiconductor package includes a base substrate, interposer package, and semiconductor chips.
  • The interposer package consists of a redistribution structure with insulating layers and redistribution layers.
  • A bridge chip is located on the bottom surface of the redistribution structure.
  • A connection structure with multiple wiring layers connects the semiconductor chips.
  • A bonding structure on the second insulating layer bonds the semiconductor chips to the redistribution structure.
  • The second redistribution layer contains a contact plug within an insulating layer.

Potential applications of this technology:

  • Semiconductor packaging for electronic devices.
  • Integrated circuits and microprocessors.
  • High-performance computing systems.
  • Consumer electronics such as smartphones, tablets, and laptops.

Problems solved by this technology:

  • Provides a compact and efficient semiconductor packaging solution.
  • Enables high-speed and reliable electrical connections between semiconductor chips.
  • Reduces signal losses and improves overall performance.
  • Enhances thermal management and heat dissipation.

Benefits of this technology:

  • Improved functionality and performance of electronic devices.
  • Increased miniaturization and integration of semiconductor chips.
  • Enhanced reliability and durability of semiconductor packages.
  • Cost-effective manufacturing and assembly processes.


Original Abstract Submitted

A semiconductor package is provided and includes: a base substrate; an interposer package on the base substrate; and first and second semiconductor chips on the interposer package, wherein the interposer package includes: a first redistribution structure including a first insulating layer, a second insulating layer on the first insulating layer, and first and second redistribution layers respectively disposed on the first and second insulating layers; a bridge chip on a bottom surface of the first redistribution structure; a connection structure on the bottom surface of the first redistribution structure and including a plurality of wiring layers electrically connected to the first and second semiconductor chips; and a bonding structure disposed on a third insulating layer on the second insulating layer and bonding each of the first and second semiconductor chips to the first redistribution structure, wherein the second redistribution layer includes a contact plug within the third insulating layer.