18136017. CLOCK SELECTION METHOD FOR MULTIPLYING DELAY LOCKED LOOP simplified abstract (Samsung Electronics Co., Ltd.)

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CLOCK SELECTION METHOD FOR MULTIPLYING DELAY LOCKED LOOP

Organization Name

Samsung Electronics Co., Ltd.

Inventor(s)

Venkatasuryam Setty Issa of Bengaluru (IN)

Aswani Aditya Kumar Tadinada of Bengaluru (IN)

Subba Reddy Siddamurthy of Bengaluru (IN)

CLOCK SELECTION METHOD FOR MULTIPLYING DELAY LOCKED LOOP - A simplified explanation of the abstract

This abstract first appeared for US patent application 18136017 titled 'CLOCK SELECTION METHOD FOR MULTIPLYING DELAY LOCKED LOOP

Simplified Explanation

The abstract of the patent application describes a method for generating a select signal for a multiplexer in a Multiplying Delay Locked Loop (MDLL). The method involves determining the output of a divider in the MDLL is at a high level, determining that the output signal of a multiplexed voltage controlled oscillator (VCO) in the MDLL is a falling edge after the divider output is at the high level, and inserting a select signal as a select input to the multiplexer at the falling edge of the multiplexed VCO output when the divider output reaches the high level.

  • The patent describes a method for generating a select signal for a multiplexer in a Multiplying Delay Locked Loop (MDLL).
  • The method involves determining the output of a divider in the MDLL is at a high level.
  • The method further involves determining that the output signal of a multiplexed VCO in the MDLL is a falling edge after the divider output is at the high level.
  • The method includes inserting a select signal as a select input to the multiplexer at the falling edge of the multiplexed VCO output when the divider output reaches the high level.

Potential applications of this technology:

  • This technology can be used in communication systems that require precise timing synchronization, such as wireless networks, satellite communication systems, and cellular networks.
  • It can also be applied in high-speed data transmission systems, where accurate timing is crucial for data integrity.

Problems solved by this technology:

  • The method provides a reliable and accurate way to generate a select signal for a multiplexer in a MDLL, ensuring precise timing synchronization in communication systems.
  • It solves the problem of timing errors and synchronization issues that can occur in multiplexing systems.

Benefits of this technology:

  • The method improves the overall performance and reliability of communication systems by providing accurate timing synchronization.
  • It allows for efficient multiplexing of signals, reducing the risk of data corruption or loss.
  • The technology can be implemented in existing systems without requiring significant modifications or additional hardware.


Original Abstract Submitted

There is provided a method for generating a select signal for a multiplexer of a Multiplying Delay Locked Loop (MDLL). The method includes determining that an output of a divider of the MDLL is a high level, determining that an output signal of a multiplexed voltage controlled oscillator (VCO) of the MDLL is a falling edge after the output of the divider is the high level and inserting a select signal as a select input to the multiplexer at the falling edge of the output signal of the multiplexed VCO in response to determining that the output of the divider has achieved the high level.

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