18135541. SEMICONDUCTOR PACKAGE AND METHOD FOR MANUFACTURING THE SEMICONDUCTOR PACKAGE simplified abstract (Samsung Electronics Co., Ltd.)
Contents
SEMICONDUCTOR PACKAGE AND METHOD FOR MANUFACTURING THE SEMICONDUCTOR PACKAGE
Organization Name
Inventor(s)
Hwanyoung Choi of Suwon-si (KR)
SEMICONDUCTOR PACKAGE AND METHOD FOR MANUFACTURING THE SEMICONDUCTOR PACKAGE - A simplified explanation of the abstract
This abstract first appeared for US patent application 18135541 titled 'SEMICONDUCTOR PACKAGE AND METHOD FOR MANUFACTURING THE SEMICONDUCTOR PACKAGE
Simplified Explanation
The semiconductor package described in the patent application includes several components and structures:
- Substrate: The package has a substrate, which serves as a base for the other components.
- Circuit layer: This layer is located on the lower surface of the substrate and contains an interconnection structure.
- First redistribution structure: Positioned adjacent to the circuit layer, this structure includes a first redistribution layer.
- Connection structure: It consists of a first connection via electrically connected to the first redistribution layer, a second connection via electrically connected to the interconnection structure, and a connection interconnection that connects the first and second connection vias.
- Semiconductor chip: Located below the first redistribution structure, the chip is electrically connected to the first redistribution layer.
- First vertical connection structure: Positioned on the lower surface of the circuit layer.
- Second vertical connection structure: Located on the lower surface of the connection structure.
- Second redistribution structure: Positioned below the semiconductor chip and the first and second vertical connection structures.
Potential applications of this technology:
- Integrated circuits: The semiconductor package can be used in various integrated circuit applications, such as microprocessors, memory chips, and sensors.
- Electronics manufacturing: This technology can be employed in the production of electronic devices, including smartphones, computers, and automotive electronics.
Problems solved by this technology:
- Improved electrical connectivity: The various connection structures and redistribution layers ensure efficient electrical connections between different components, enhancing the overall performance of the semiconductor package.
- Space optimization: The vertical connection structures and redistribution layers allow for compact packaging of the semiconductor chip and other components, enabling more efficient use of space.
Benefits of this technology:
- Enhanced performance: The improved electrical connectivity results in better signal transmission and reduced signal loss, leading to improved performance of the semiconductor package.
- Space-saving design: The compact packaging achieved through the vertical connection structures and redistribution layers allows for smaller and more lightweight electronic devices.
- Cost-effective manufacturing: The technology enables efficient manufacturing processes, reducing production costs and increasing overall profitability.
Original Abstract Submitted
A semiconductor package includes: a substrate; a circuit layer disposed on a lower surface of the substrate, the circuit layer including an interconnection structure; a first redistribution structure disposed adjacent to the circuit layer, the first redistribution structure including a first redistribution layer; a connection structure including a first connection via electrically connected to the first redistribution layer, a second connection via electrically connected to the interconnection structure, and a connection interconnection interconnecting the first and second connection vias; a semiconductor chip disposed below the first redistribution structure, and electrically connected to the first redistribution layer; a first vertical connection structure disposed on a lower surface of the circuit layer; a second vertical connection structure disposed on a lower surface of the connection structure; and a second redistribution structure disposed below the semiconductor chip and the first and second vertical connection structures.
