18135349. THREE-DIMENSIONAL SEMICONDUCTOR MEMORY DEVICE AND ELECTRONIC SYSTEM INCLUDING THE SAME simplified abstract (SAMSUNG ELECTRONICS CO., LTD.)
THREE-DIMENSIONAL SEMICONDUCTOR MEMORY DEVICE AND ELECTRONIC SYSTEM INCLUDING THE SAME
Organization Name
Inventor(s)
Sung-Min Hwang of Suwon-si (KR)
Seunghyun Cho of Suwon-si (KR)
THREE-DIMENSIONAL SEMICONDUCTOR MEMORY DEVICE AND ELECTRONIC SYSTEM INCLUDING THE SAME - A simplified explanation of the abstract
This abstract first appeared for US patent application 18135349 titled 'THREE-DIMENSIONAL SEMICONDUCTOR MEMORY DEVICE AND ELECTRONIC SYSTEM INCLUDING THE SAME
Simplified Explanation
The semiconductor memory device described in the patent application includes a gate stack structure with insulating layers, a lower selection line, and word lines. The word lines consist of a first word line next to the lower selection line and a second word line above the first word line. Additionally, there is a memory channel structure that goes through the gate stack structure, along with multiple first contact plugs connected to the first word line, and multiple second contact plugs connected to the second word line. A first conductive line is linked to the first contact plugs, and a second conductive line is connected to one of the second contact plugs.
- Gate stack structure with insulating layers, lower selection line, and word lines
- Memory channel structure penetrating the gate stack structure
- First and second word lines with corresponding contact plugs
- First conductive line connected to first contact plugs
- Second conductive line connected to one of the second contact plugs
Potential Applications
- Semiconductor memory devices
- Integrated circuits
- Data storage systems
Problems Solved
- Efficient data storage and retrieval
- Improved memory access speed
- Enhanced reliability of memory devices
Benefits
- Higher performance in data processing
- Increased storage capacity
- Enhanced overall system efficiency
Original Abstract Submitted
A semiconductor memory device includes a gate stack structure including insulating layers, a lower selection line and word lines, the word lines including a first word line adjacent to the lower selection line and a second word line on the first word line, a memory channel structure penetrating the gate stack structure, a plurality of first contact plugs electrically connected to the first word line, a plurality of second contact plugs electrically connected to the second word line, a first conductive line connected to the plurality of first contact plugs, and a second conductive line connected to one of the plurality of second contact plugs.
