18132749. SEMICONDUCTOR PACKAGE simplified abstract (SAMSUNG ELECTRONICS CO., LTD.)
Contents
SEMICONDUCTOR PACKAGE
Organization Name
Inventor(s)
SEMICONDUCTOR PACKAGE - A simplified explanation of the abstract
This abstract first appeared for US patent application 18132749 titled 'SEMICONDUCTOR PACKAGE
Simplified Explanation
The abstract describes a semiconductor package that includes two semiconductor chips stacked on top of each other. The first chip has an upper pad and a polymer layer on its upper surface. The second chip is mounted on top of the first chip and has a lower pad under its lower surface. The polymer layer has different widths in different regions of the second chip.
- The semiconductor package includes two stacked semiconductor chips.
- The first chip has an upper pad and a polymer layer on its upper surface.
- The second chip is mounted on top of the first chip.
- The second chip has a lower pad under its lower surface.
- The polymer layer has different widths in different regions of the second chip.
Potential Applications:
- Semiconductor packaging industry
- Electronics manufacturing
Problems Solved:
- Efficient stacking of semiconductor chips
- Improved electrical connections between chips
Benefits:
- Compact design
- Enhanced performance
- Cost-effective manufacturing
Original Abstract Submitted
A semiconductor package includes a first semiconductor chip including a first semiconductor substrate, and a first upper pad arranged on an upper surface of the first semiconductor substrate, a first polymer layer arranged on the upper surface of the first semiconductor substrate, a second semiconductor chip mounted on the first semiconductor chip, the second semiconductor chip including a second semiconductor substrate and a second lower pad arranged under a lower surface of the second semiconductor substrate, wherein the first polymer layer has a horizontal width in a direction crossing the first polymer layer in a center region of the second semiconductor chip, as a first length, and has a horizontal width in a direction crossing two corner regions of the first polymer layer in corner regions of the second semiconductor chip, as a second length, wherein the second length is greater than the first length.
