18126267. MEMORY DEVICE AND METHOD OF TESTING THE MEMORY DEVICE FOR FAILURE simplified abstract (SK hynix Inc.)

MEMORY DEVICE AND METHOD OF TESTING THE MEMORY DEVICE FOR FAILURE

Organization Name

SK hynix Inc.

Inventor(s)

Byung Wook Bae of Icheon-si Gyeonggi-do (KR)

Jung Ryul Ahn of Icheon-si Gyeonggi-do (KR)

MEMORY DEVICE AND METHOD OF TESTING THE MEMORY DEVICE FOR FAILURE - A simplified explanation of the abstract

This abstract first appeared for US patent application 18126267 titled 'MEMORY DEVICE AND METHOD OF TESTING THE MEMORY DEVICE FOR FAILURE

Simplified Explanation

The patent application describes a memory device and a method of testing the memory device for failure. The device includes a first chip with a memory cell array and a second chip overlapping with the first chip. The second chip includes a semiconductor substrate with a peripheral circuit area and a lower test area, sub-test pads, sub-test circuits, and a detection circuit.

• The memory device includes a first chip with a memory cell array and a second chip with a peripheral circuit area and a lower test area.
• The second chip has sub-test pads and sub-test circuits connected to these pads for testing purposes.
• A detection circuit is connected to the sub-test circuits to output a detection signal based on input signals from the terminals.

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1. 1. 1. Potential Applications

This technology can be used in the manufacturing and testing of memory devices, ensuring quality control and reliability in memory products.

1. 1. 1. Problems Solved

This technology helps in detecting failures in memory devices during testing, allowing for defective units to be identified and rectified before they reach the market.

1. 1. 1. Benefits

The method described in the patent application improves the efficiency and accuracy of testing memory devices, leading to higher quality products and increased customer satisfaction.

1. 1. 1. Potential Commercial Applications

This technology can be applied in the semiconductor industry for the production of memory devices, enhancing the testing process and overall product quality.

1. 1. 1. Possible Prior Art

One possible prior art could be the use of sub-test circuits in memory devices for testing purposes. However, the specific configuration and integration described in this patent application may be novel and inventive.

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1. 1. 1. 1. Unanswered Questions

1. 1. 1. How does this technology compare to existing memory device testing methods?

This article does not provide a direct comparison to existing memory device testing methods, leaving the reader to wonder about the specific advantages and disadvantages of this new approach.

1. 1. 1. What are the specific technical specifications of the memory cell array and sub-test circuits in this technology?

The article does not delve into the technical details of the memory cell array and sub-test circuits, leaving readers curious about the specific design and functionality of these components.

Original Abstract Submitted

A memory device, and a method of testing the memory device for failure, includes a first chip including a memory cell array and a second chip overlapping with the first chip. The second chip includes: a semiconductor substrate including a peripheral circuit area and a lower test area; a plurality of sub-test pads and an input pad, disposed on the lower test area of the semiconductor substrate and spaced apart from each other; a plurality of sub-test circuits respectively connected to the plurality of sub-test pads; and a detection circuit connected to a plurality of terminals of the plurality of sub-test circuits, the detection circuit configured to output a detection signal changed according to a plurality of signals input from the plurality of terminals.