18125928. SEMICONDUCTOR PACKAGE simplified abstract (SAMSUNG ELECTRONICS CO., LTD.)
Contents
SEMICONDUCTOR PACKAGE
Organization Name
Inventor(s)
Wonkyoung Choi of Suwon-si (KR)
SEMICONDUCTOR PACKAGE - A simplified explanation of the abstract
This abstract first appeared for US patent application 18125928 titled 'SEMICONDUCTOR PACKAGE
Simplified Explanation
The semiconductor package described in the patent application consists of a lower package, an upper package, and an inter-package connector. The lower package includes a redistribution structure, on which two semiconductor chips are mounted. A molding layer is present on the redistribution structure and in contact with the side walls of both semiconductor chips. A conductive post passes through the molding layer and is electrically connected to one of the semiconductor chips through a redistribution pattern.
- The lower package of the semiconductor package includes a redistribution structure, on which multiple semiconductor chips can be mounted.
- A molding layer is applied on the redistribution structure, providing protection and electrical insulation.
- The conductive post passing through the molding layer allows for electrical connection to one of the semiconductor chips.
- The upper package is positioned on top of the molding layer, overlapping with the area where the second semiconductor chip is mounted, but not covering the first semiconductor chip.
Potential Applications:
- This semiconductor package design can be used in various electronic devices that require multiple semiconductor chips to be mounted and connected.
- It can be applied in the fields of consumer electronics, telecommunications, automotive, and industrial applications.
Problems Solved:
- The inter-package connector provides a reliable electrical connection between the lower and upper packages, ensuring proper functionality of the semiconductor chips.
- The molding layer protects the semiconductor chips from external factors such as moisture, dust, and physical damage.
- The design allows for efficient use of space, as the upper package does not cover the first semiconductor chip.
Benefits:
- Improved reliability and performance of electronic devices by ensuring proper electrical connections between semiconductor chips.
- Enhanced protection of semiconductor chips from environmental factors, leading to increased lifespan and durability of the device.
- Space-saving design allows for more compact and efficient electronic devices.
Original Abstract Submitted
A semiconductor package includes a lower package, an upper package on the lower package, and an inter-package connector between the lower package and the upper package. The lower package includes a first redistribution structure, a first semiconductor chip mounted on a first mounting region of the first redistribution structure, a second semiconductor chip mounted on a second mounting region of the first redistribution structure, a molding layer on the first redistribution structure and in contact with a side wall of the first semiconductor chip and a side wall of the second semiconductor chip, and a conductive post passing through the molding layer and electrically connected to the first semiconductor chip through a first redistribution pattern of the first redistribution structure. The upper package is on the molding layer, vertically overlaps with the second mounting region of the first redistribution structure, and does not cover the first semiconductor chip.
