18121374. SEMICONDUCTOR PACKAGE simplified abstract (Samsung Electronics Co., Ltd.)
Contents
SEMICONDUCTOR PACKAGE
Organization Name
Inventor(s)
Yanggyoo Jung of Suwon-si (KR)
Younglyong Kim of Suwon-si (KR)
SEMICONDUCTOR PACKAGE - A simplified explanation of the abstract
This abstract first appeared for US patent application 18121374 titled 'SEMICONDUCTOR PACKAGE
Simplified Explanation
The abstract describes a semiconductor package that includes a package substrate, multiple semiconductor chips, multiple interposers, and a molding layer. The semiconductor chips are arranged horizontally, with the second and third chips spaced apart from the first chip. The interposers include vertical connection interposers overlapping the respective semiconductor chips and horizontal connection interposers overlapping multiple semiconductor chips.
- The semiconductor package includes multiple semiconductor chips arranged horizontally.
- Interposers are used to connect the semiconductor chips and the package substrate.
- The interposers include vertical connection interposers and horizontal connection interposers.
- The molding layer is in contact with the semiconductor chips and interposers.
Potential applications of this technology:
- Semiconductor packaging for electronic devices such as smartphones, tablets, and computers.
- High-performance computing systems that require efficient interconnection between semiconductor chips.
Problems solved by this technology:
- Provides a compact and efficient solution for connecting multiple semiconductor chips in a package.
- Enables vertical and horizontal connections between the chips and the package substrate.
Benefits of this technology:
- Improved performance and reliability of semiconductor packages.
- Enhanced thermal management due to efficient interposer design.
- Cost-effective solution for semiconductor packaging.
Original Abstract Submitted
In some embodiments, a semiconductor package includes a package substrate, a plurality of semiconductor chips on the package substrate, a plurality of interposers between the package substrate and the plurality of semiconductor chips, and a molding layer in contact with the plurality of semiconductor chips and the plurality of interposers. The plurality of semiconductor chips includes a first semiconductor chip, and a second and a third semiconductor chip spaced apart from the first semiconductor chip in horizontal directions. The plurality of interposers includes a first vertical connection interposer vertically overlapping the first semiconductor chip, a second vertical connection interposer vertically overlapping the second semiconductor chip, a first horizontal connection interposer vertically overlapping the first and the second semiconductor chips, and a second horizontal connection interposer vertically overlapping the second and the third semiconductor chips.
