18120845. SEMICONDUCTOR DEVICES simplified abstract (Samsung Electronics Co., Ltd.)

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SEMICONDUCTOR DEVICES

Organization Name

Samsung Electronics Co., Ltd.

Inventor(s)

Seulki Hong of Suwon-si (KR)

Youghan Kim of Suwon-si (KR)

Jaeyeop Lee of Suwon-si (KR)

SEMICONDUCTOR DEVICES - A simplified explanation of the abstract

This abstract first appeared for US patent application 18120845 titled 'SEMICONDUCTOR DEVICES

Simplified Explanation

The abstract describes a semiconductor device that includes a first gate structure, a first source/drain layer, and a first contact plug. The device is formed on a substrate and has specific structural features.

  • The first gate structure is formed on the substrate and extends parallel to the substrate's upper surface.
  • The first source/drain layer is located at the side of the first gate structure and runs parallel to the substrate's upper surface in a direction that crosses the gate structure.
  • The upper surface of the first source/drain layer has a central portion and an edge portion in the direction mentioned earlier.
  • The central portion of the first source/drain layer's upper surface is lower than the edge portion.
  • The first contact plug is formed on the first source/drain layer and makes contact with the edge portion of its upper surface.

Potential applications of this technology:

  • Semiconductor devices: This innovation can be applied to various semiconductor devices, such as transistors, integrated circuits, and microprocessors.
  • Electronics manufacturing: The technology can be utilized in the manufacturing process of electronic devices to improve their performance and functionality.

Problems solved by this technology:

  • Improved device performance: The specific structural features described in the patent application can enhance the performance of semiconductor devices by optimizing the contact between different layers and improving electrical conductivity.
  • Reduction of parasitic resistance: The lower central portion of the first source/drain layer's upper surface helps minimize parasitic resistance, leading to better device performance.

Benefits of this technology:

  • Enhanced device functionality: By improving the contact between different layers, the technology can enhance the overall functionality and performance of semiconductor devices.
  • Increased efficiency: The reduction of parasitic resistance contributes to increased efficiency and improved power consumption in electronic devices.
  • Manufacturing optimization: The specific structural features described in the patent application can be implemented in the manufacturing process to optimize the production of semiconductor devices.


Original Abstract Submitted

A semiconductor device includes a first gate structure, a first source/drain layer and a first contact plug. The first gate structure is formed on a substrate, and extends in a second direction parallel to an upper surface of the substrate. The first source/drain layer is formed at a side of the first gate structure in a first direction substantially parallel to the upper surface of the substrate and crossing the second direction. A central portion in the first direction of an upper surface of the first source/drain layer is lower than an edge portion in the first direction of the upper surface of the first source/drain layer. The first contact plug is formed on the first source/drain layer, and contacts the edge portion of the upper surface of the first source/drain layer.