18120826. SEMICONDUCTOR CHIP, SEMICONDUCTOR PACKAGE INCLUDING THE SAME, AND METHOD OF FABRICATING THE SAME simplified abstract (Samsung Electronics Co., Ltd.)
Contents
SEMICONDUCTOR CHIP, SEMICONDUCTOR PACKAGE INCLUDING THE SAME, AND METHOD OF FABRICATING THE SAME
Organization Name
Inventor(s)
Young kun Jee of Suwon-si (KR)
SEMICONDUCTOR CHIP, SEMICONDUCTOR PACKAGE INCLUDING THE SAME, AND METHOD OF FABRICATING THE SAME - A simplified explanation of the abstract
This abstract first appeared for US patent application 18120826 titled 'SEMICONDUCTOR CHIP, SEMICONDUCTOR PACKAGE INCLUDING THE SAME, AND METHOD OF FABRICATING THE SAME
Simplified Explanation
The semiconductor chip described in the patent application includes:
- A semiconductor substrate with first and second surfaces
- A transistor on the first surface
- A first interlayer dielectric layer on the transistor
- A second interlayer dielectric layer on the first interlayer dielectric layer
- A wiring line in the second interlayer dielectric layer
- A first conductive pad on the second interlayer dielectric layer
- A first passivation layer on the second interlayer dielectric layer
- A second conductive pad in the first passivation layer
- A through via connecting the wiring line to the second surface
- A second passivation layer on the second surface
- A third conductive pad in the second passivation layer connected to the through via
Potential applications of this technology:
- Integrated circuits
- Semiconductor devices
- Electronic components
Problems solved by this technology:
- Improved interconnection reliability
- Enhanced performance of semiconductor chips
- Increased durability of electronic devices
Benefits of this technology:
- Higher efficiency in data processing
- Reduced risk of signal interference
- Longer lifespan of electronic products
Original Abstract Submitted
A semiconductor chip including a semiconductor substrate having first and second surfaces, a transistor on the first surface, a first interlayer dielectric layer on the transistor, a second interlayer dielectric layer on the first interlayer dielectric layer, a wiring line in the second interlayer dielectric layer, a first conductive pad on the second interlayer dielectric layer, a first passivation layer on the second interlayer dielectric layer, a second conductive pad in the first passivation layer, a through via penetrating the semiconductor substrate and the first interlayer dielectric layer to come into connection with the wiring line, a second passivation layer on the second surface, and a third conductive pad in the second passivation layer and connected to the through via. The first passivation layer has a first thickness 0.4 to 0.6 times a second thickness between the first surface and a top surface of the second passivation layer.
