18119458. MEMORY DEVICE AND OPERATION METHOD THEREOF simplified abstract (Samsung Electronics Co., Ltd.)
Contents
- 1 MEMORY DEVICE AND OPERATION METHOD THEREOF
- 1.1 Organization Name
- 1.2 Inventor(s)
- 1.3 MEMORY DEVICE AND OPERATION METHOD THEREOF - A simplified explanation of the abstract
- 1.4 Simplified Explanation
- 1.5 Potential Applications
- 1.6 Problems Solved
- 1.7 Benefits
- 1.8 Potential Commercial Applications
- 1.9 Possible Prior Art
- 1.10 Original Abstract Submitted
MEMORY DEVICE AND OPERATION METHOD THEREOF
Organization Name
Inventor(s)
Seung-jun Lee of Suwon-si (KR)
MEMORY DEVICE AND OPERATION METHOD THEREOF - A simplified explanation of the abstract
This abstract first appeared for US patent application 18119458 titled 'MEMORY DEVICE AND OPERATION METHOD THEREOF
Simplified Explanation
The memory device described in the patent application includes multiple banks that perform a per-bank refresh (PBR) operation, as well as an address register that provides a single row address signal to two banks simultaneously. The two banks share the single row address signal and activate a word line of each memory cell array based on a single decoded row address signal generated from this shared signal.
- Two banks perform per-bank refresh (PBR) operation simultaneously
- Address register provides single row address signal to two banks
- Shared single row address signal used to activate word lines of memory cell arrays
Potential Applications
This technology could be applied in:
- High-speed memory devices
- Data centers
- Embedded systems
Problems Solved
This technology helps in:
- Improving memory access speed
- Enhancing memory efficiency
- Simplifying memory management
Benefits
The benefits of this technology include:
- Faster data retrieval
- Increased memory performance
- Reduced power consumption
Potential Commercial Applications
This technology could be commercially benefit:
- Memory chip manufacturers
- Computer hardware companies
- Data storage companies
Possible Prior Art
One possible prior art could be the use of shared row address signals in memory devices to improve efficiency and speed.
Unanswered Questions
How does this technology impact overall system performance?
This technology can significantly improve system performance by enhancing memory access speed and efficiency.
What are the potential cost implications of implementing this technology?
The cost implications of implementing this technology could include initial investment in new memory devices and potential savings in energy consumption over time.
Original Abstract Submitted
A memory device includes plural banks that perform a per-bank refresh (PBR) operation, and an address register that provides a single row address signal to two banks of the plural banks, the two banks simultaneously performing the PBR operation and the single row address signal being shared by the two banks. The two banks activate a word line of each memory cell array based on a single decoded row address signal that is generated based on the single row address signal.
