18117736. SEMICONDUCTOR PACKAGE simplified abstract (Samsung Electronics Co., Ltd.)

SEMICONDUCTOR PACKAGE

Organization Name

Samsung Electronics Co., Ltd.

Inventor(s)

Seok Geun Ahn of Suwon-si (KR)

Hwanyoung Choi of Suwon-si (KR)

SEMICONDUCTOR PACKAGE - A simplified explanation of the abstract

This abstract first appeared for US patent application 18117736 titled 'SEMICONDUCTOR PACKAGE

Simplified Explanation

The semiconductor package described in the patent application consists of multiple layers and chips connected together. Here is a simplified explanation of the abstract:

• The package includes a first lower redistribution layer, a first upper redistribution layer, and a first semiconductor chip placed between them.
• A first connection post is used to connect the first lower redistribution layer to the first upper redistribution layer.
• A first interposition layer is added on top of the first upper redistribution layer.
• A second interposition layer is added on top of the first interposition layer.
• A second lower redistribution layer is placed on the second interposition layer.
• A second upper redistribution layer is added on top of the second lower redistribution layer.
• A second semiconductor chip is placed between the second lower redistribution layer and the second upper redistribution layer.
• Two second connection posts are used to connect the second lower redistribution layer to the second upper redistribution layer.

Potential applications of this technology:

• Integrated circuits: This semiconductor package can be used in various integrated circuits, such as microprocessors, memory chips, and sensors.
• Electronics manufacturing: The package can be utilized in the manufacturing of electronic devices, including smartphones, computers, and IoT devices.

Problems solved by this technology:

• Space optimization: The use of multiple layers and chips allows for efficient use of space within the semiconductor package.
• Improved connectivity: The connection posts ensure reliable connections between the redistribution layers and semiconductor chips.

Benefits of this technology:

• Higher performance: The design of the semiconductor package enables improved performance of integrated circuits.
• Enhanced reliability: The reliable connections provided by the connection posts contribute to the overall reliability of the package.
• Cost-effective manufacturing: The use of multiple layers and chips can lead to cost savings in the manufacturing process.

Original Abstract Submitted

A semiconductor package includes a first lower redistribution layer, a first upper redistribution layer over the first lower redistribution layer, a first semiconductor chip between the first lower redistribution layer and the first upper redistribution layer, a first connection post spaced apart from the first semiconductor chip and connecting the first lower redistribution layer to the first upper redistribution layer, a first interposition layer on the first upper redistribution layer, a second interposition layer on the first interposition layer, a second lower redistribution layer on the second interposition layer, a second upper redistribution layer over the second lower redistribution layer, a second semiconductor chip between the second lower redistribution layer and the second upper redistribution layer, and a second connection post spaced apart from each other and connecting the second lower redistribution layer to the second upper redistribution layer.