18116414. SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME simplified abstract (SAMSUNG ELECTRONICS CO., LTD.)

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SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME

Organization Name

SAMSUNG ELECTRONICS CO., LTD.

Inventor(s)

Woon Chun Kim of Suwon-si (KR)

Dae Seo Park of Suwon-si (KR)

Jumyong Park of Suwon-si (KR)

SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - A simplified explanation of the abstract

This abstract first appeared for US patent application 18116414 titled 'SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME

Simplified Explanation

The semiconductor device described in the patent application consists of a lower structure and an upper structure. The lower structure includes a first semiconductor substrate, a first pad, and a first dielectric layer. The upper structure includes a second semiconductor substrate, a second pad, and a second dielectric layer. The first and second pads are bonded together across an interfacial layer to connect the upper and lower structures.

  • The first and second pads, as well as the interfacial layer, are made of the same metallic material.
  • The first and second pads have a substantially similar average grain size, while the interfacial layer has a different average grain size.

Potential applications of this technology:

  • This semiconductor device can be used in various electronic devices such as smartphones, computers, and integrated circuits.
  • It can improve the performance and reliability of these devices by providing a strong and efficient connection between the upper and lower structures.

Problems solved by this technology:

  • The bonding between the upper and lower structures is enhanced by using pads and an interfacial layer with specific grain sizes.
  • This helps to prevent delamination and improve the overall structural integrity of the semiconductor device.

Benefits of this technology:

  • The use of the same metallic material for the pads and interfacial layer ensures compatibility and reduces the risk of material incompatibility issues.
  • The optimized grain sizes of the pads and interfacial layer improve the bonding strength and reliability of the semiconductor device.
  • This technology can lead to more robust and efficient electronic devices with improved performance and longevity.


Original Abstract Submitted

A semiconductor device includes a lower structure and an upper structure on the lower structure. The lower structure includes a first semiconductor substrate, a first pad and a first dielectric layer. The first dielectric layer surrounds the first pad and exposes a top surface of the first pad. The upper structure includes a second semiconductor substrate, a second pad and a second dielectric layer. The second dielectric layer surrounds the second pad and exposes a bottom surface of the second pad. The first pad and the second pad are bonded to each other across an interfacial layer to couple the upper and lower structures to each other. The first and second pads and the interfacial layer include a same metallic material. The first and second pads have a substantially same average grain size and the interfacial layer has a different average grain size than the first and second pads.

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