18115891. METHOD AND APPARATUS WITH 3D IN-MEMORY COMPUTING simplified abstract (Samsung Electronics Co., Ltd.)
Contents
- 1 METHOD AND APPARATUS WITH 3D IN-MEMORY COMPUTING
- 1.1 Organization Name
- 1.2 Inventor(s)
- 1.3 METHOD AND APPARATUS WITH 3D IN-MEMORY COMPUTING - A simplified explanation of the abstract
- 1.4 Simplified Explanation
- 1.5 Potential Applications
- 1.6 Problems Solved
- 1.7 Benefits
- 1.8 Potential Commercial Applications
- 1.9 Possible Prior Art
- 1.10 Original Abstract Submitted
METHOD AND APPARATUS WITH 3D IN-MEMORY COMPUTING
Organization Name
Inventor(s)
Seungchul Jung of Suwon-si (KR)
Soon-Wan Kwon of Suwon-si (KR)
METHOD AND APPARATUS WITH 3D IN-MEMORY COMPUTING - A simplified explanation of the abstract
This abstract first appeared for US patent application 18115891 titled 'METHOD AND APPARATUS WITH 3D IN-MEMORY COMPUTING
Simplified Explanation
The patent application describes an apparatus with a memory layer containing front-end-of-line (FEOL) memory cells and a logic layer with arithmetic logic gates made of back-end-of-line (BEOL) transistors stacked on top of the memory cells. The BEOL transistors function as multipliers, providing operation results based on values stored in the memory cells.
- The apparatus includes a memory layer with FEOL memory cells and a logic layer with BEOL transistors.
- BEOL transistors are vertically stacked on top of the memory cells and operate as multipliers.
- The BEOL transistors provide operation results based on values stored in the corresponding memory cells.
Potential Applications
This technology could be applied in:
- High-performance computing systems
- Signal processing applications
- Artificial intelligence and machine learning algorithms
Problems Solved
This technology addresses:
- Increasing demand for faster and more efficient computation
- Need for compact and integrated memory and logic components
- Improving overall system performance and energy efficiency
Benefits
The benefits of this technology include:
- Enhanced computational speed and efficiency
- Reduced power consumption
- Compact and integrated design for space-saving solutions
Potential Commercial Applications
The potential commercial applications of this technology could be in:
- Data centers
- Mobile devices
- Automotive electronics
Possible Prior Art
One possible prior art for this technology could be the use of stacked transistors in memory and logic integration in semiconductor devices.
Unanswered Questions
How does this technology compare to traditional memory and logic integration methods?
This article does not provide a direct comparison between this technology and traditional methods of memory and logic integration. Further research and analysis would be needed to determine the specific advantages and disadvantages of this approach.
What are the scalability limitations of this technology in terms of the number of memory cells and logic gates that can be integrated?
The article does not address the scalability limitations of this technology in terms of the maximum number of memory cells and logic gates that can be integrated. Additional studies and experiments would be required to determine the scalability of this approach.
Original Abstract Submitted
An apparatus including a memory layer including a plurality of front-end-of-line (FEOL) memory cells and a logic layer including plural arithmetic logic gates including back-end-of-line (BEOL) transistors, the plurality of BEOL transistors being vertically stacked on respective upper ends of the plurality of memory cells, wherein each of multiple transistors of the plurality of BEOL transistors operates as a multiplier and is configured to provide an operation result with respect to first values stored in corresponding memory cells of the plurality of memory cells.
