18113163. SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SAME simplified abstract (Samsung Electronics Co., Ltd.)
Contents
SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SAME
Organization Name
Inventor(s)
Jung-Seok Ahn of Suwon-si (KR)
Hyeong Mun Kang of Suwon-si (KR)
Seung Woo Sim of Suwon-si (KR)
SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SAME - A simplified explanation of the abstract
This abstract first appeared for US patent application 18113163 titled 'SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SAME
Simplified Explanation
The abstract describes a semiconductor package that includes a substrate with two regions, a wiring pattern on the first surface of the substrate, a first recess on the second surface of the substrate, a back side insulating layer that fills the first recess, a through via that connects to the wiring pattern and penetrates through the substrate and the back side insulating layer, and a second recess formed in the back side insulating layer on top of the first recess.
- The substrate has two regions, with one region partially surrounding the other.
- The first surface of the substrate has a wiring pattern.
- The second surface of the substrate has a first recess.
- The back side insulating layer is disposed on the second surface of the substrate and fills the first recess.
- The through via connects to the wiring pattern and penetrates through the substrate and the back side insulating layer.
- The second recess is formed in the back side insulating layer on top of the first recess.
Potential applications of this technology:
- Semiconductor packaging for integrated circuits.
- Electronic devices requiring compact and efficient wiring connections.
Problems solved by this technology:
- Provides a compact and efficient wiring solution for semiconductor packages.
- Helps in reducing the size and complexity of electronic devices.
Benefits of this technology:
- Improved electrical connectivity and signal transmission.
- Enhanced reliability and performance of semiconductor packages.
- Enables miniaturization of electronic devices.
Original Abstract Submitted
A semiconductor package includes: a substrate including a first region and a second region at least partially surrounding the first region in a plane defined by first and second horizontal directions, wherein the substrate has a first surface and a second surface opposed to the first surface; a wiring pattern disposed on the first surface of the substrate; a first recess formed on the second surface of the substrate and in the second region of the substrate; a back side insulating layer disposed on the second surface of the substrate, wherein the back side insulating layer fills an inside of the first recess; a through via penetrating through the first region of the substrate and the back side insulating layer, wherein the through via connects to the wiring pattern; and a second recess formed in the back side insulating layer and on the first recess.