18109392. SEMICONDUCTOR PACKAGE simplified abstract (SAMSUNG ELECTRONICS CO., LTD.)
Contents
SEMICONDUCTOR PACKAGE
Organization Name
Inventor(s)
Myungsam Kang of Suwon-si (KR)
SEMICONDUCTOR PACKAGE - A simplified explanation of the abstract
This abstract first appeared for US patent application 18109392 titled 'SEMICONDUCTOR PACKAGE
Simplified Explanation
The semiconductor package described in the patent application consists of a connection substrate with a cavity, a first semiconductor chip, a second semiconductor chip, and a third semiconductor chip. The first and second semiconductor chips are placed on the connection substrate, while the third semiconductor chip is located within the cavity of the connection substrate. The first and second semiconductor chips are connected to each other through the third semiconductor chip. Additionally, there is a molding layer that covers all three semiconductor chips, with the first bumps of the third semiconductor chip exposed through the molding layer and connected to the first and second semiconductor chips.
- The patent application describes a semiconductor package with multiple chips connected to each other through a third chip.
- The connection substrate has a cavity that houses the third semiconductor chip.
- The first and second semiconductor chips are placed on top of the connection substrate.
- The third semiconductor chip includes exposed first bumps that connect it to the first and second semiconductor chips.
- A molding layer covers all three semiconductor chips.
Potential applications of this technology:
- Integrated circuits: The semiconductor package can be used in various integrated circuit applications where multiple chips need to be connected and housed within a single package.
- Electronics manufacturing: This technology can be utilized in the manufacturing of electronic devices that require compact and efficient packaging of multiple semiconductor chips.
Problems solved by this technology:
- Space optimization: The semiconductor package allows for the efficient use of space by housing multiple chips within a single package.
- Chip connectivity: The first and second semiconductor chips are connected to each other through the third semiconductor chip, ensuring reliable and efficient communication between the chips.
Benefits of this technology:
- Compact design: The semiconductor package offers a compact design by integrating multiple chips within a single package.
- Improved performance: The connectivity between the chips through the third semiconductor chip enhances the overall performance of the semiconductor package.
- Cost-effective: The integration of multiple chips within a single package reduces manufacturing and assembly costs.
Original Abstract Submitted
A semiconductor package includes a connection substrate with a cavity, a first semiconductor chip and a second semiconductor chip on the connection substrate, a third semiconductor chip in the cavity of the connection substrate, the first semiconductor chip and the second semiconductor chip being on the third semiconductor chip and being connected to each other through the third semiconductor chip, and a molding layer that covers the first semiconductor chip, the second semiconductor chip, and the third semiconductor chip, wherein the third semiconductor chip includes first bumps that are exposed through the molding layer and are connected to the first semiconductor chip and the second semiconductor chip.
