18108125. SEMICONDUCTOR DEVICES simplified abstract (Samsung Electronics Co., Ltd.)
Contents
SEMICONDUCTOR DEVICES
Organization Name
Inventor(s)
Hoonsung Choi of Suwon-si (KR)
SEMICONDUCTOR DEVICES - A simplified explanation of the abstract
This abstract first appeared for US patent application 18108125 titled 'SEMICONDUCTOR DEVICES
Simplified Explanation
The abstract describes a semiconductor device that includes a bulk substrate with two regions, a buried oxide layer, and a semiconductor layer stacked on one region. It also includes two gate structures and two source/drain layers.
- The semiconductor device has a bulk substrate with two distinct regions.
- A buried oxide layer and a semiconductor layer are stacked on one region of the bulk substrate.
- The device includes two gate structures, one on the semiconductor layer and the other on the second region of the bulk substrate.
- Two source/drain layers are located at the upper portion of the semiconductor layer and the bulk substrate, adjacent to the respective gate structures.
Potential Applications
- This semiconductor device can be used in various electronic devices such as smartphones, tablets, and computers.
- It can be utilized in the manufacturing of integrated circuits and microprocessors.
Problems Solved
- The device solves the problem of integrating multiple gate structures and source/drain layers on a single semiconductor device.
- It addresses the need for efficient and compact semiconductor devices with improved performance.
Benefits
- The device allows for the integration of multiple gate structures and source/drain layers, enabling more complex circuitry.
- It provides improved performance and efficiency in electronic devices.
- The compact design of the device allows for smaller and thinner electronic devices.
Original Abstract Submitted
A semiconductor device includes a bulk substrate including a first region and a second region, a buried oxide layer and a semiconductor layer stacked on the first region, a first gate structure disposed on the semiconductor layer, a first source/drain layer disposed at an upper portion of the semiconductor layer adjacent to the first gate structure, a second gate structure disposed on the second region, and a second source/drain layer disposed at an upper portion of the bulk substrate adjacent to the second gate structure.
