18105945. REDISTRIBUTION SUBSTRATE, METHOD OF FABRICATING THE SAME, AND SEMICONDUCTOR PACKAGE INCLUDING THE SAME simplified abstract (Samsung Electronics Co., Ltd.)
REDISTRIBUTION SUBSTRATE, METHOD OF FABRICATING THE SAME, AND SEMICONDUCTOR PACKAGE INCLUDING THE SAME
Organization Name
Inventor(s)
Seokhyun Lee of Hwaseong-si (KR)
REDISTRIBUTION SUBSTRATE, METHOD OF FABRICATING THE SAME, AND SEMICONDUCTOR PACKAGE INCLUDING THE SAME - A simplified explanation of the abstract
This abstract first appeared for US patent application 18105945 titled 'REDISTRIBUTION SUBSTRATE, METHOD OF FABRICATING THE SAME, AND SEMICONDUCTOR PACKAGE INCLUDING THE SAME
Simplified Explanation
The patent application describes a method for forming conductive patterns and vias in a semiconductor device. Here is a simplified explanation of the abstract:
- A first conductive pattern is formed.
- A photosensitive layer is applied on the first conductive pattern, with a through hole exposing a portion of the pattern.
- A first via is formed in the through hole.
- The photosensitive layer is removed.
- A dielectric layer is formed, encapsulating the first conductive pattern and first via, while exposing the top surface of the first via.
- A second conductive pattern is formed on the top surface of the first via, and a dielectric layer covers the second conductive pattern.
- The dielectric layer is etched to create a second through hole, exposing a portion of the second conductive pattern.
- A second via is formed, filling the second through hole, and an under bump pad is created on the second via.
- A semiconductor chip is mounted on the under bump pad using a connection terminal.
Potential applications of this technology:
- Semiconductor manufacturing industry
- Electronics industry
- Integrated circuit production
Problems solved by this technology:
- Efficient formation of conductive patterns and vias in a semiconductor device
- Improved connectivity and reliability in semiconductor chips
Benefits of this technology:
- Simplified and streamlined manufacturing process
- Enhanced electrical performance and connectivity in semiconductor devices
- Increased reliability and durability of semiconductor chips
Original Abstract Submitted
A method is provided and includes forming a first conductive pattern; forming a photosensitive layer on the first conductive pattern, the photosensitive layer having a first through hole exposing a portion of the first conductive pattern; forming a first via in the first through hole; removing the photosensitive layer; forming a dielectric layer encapsulating the first conductive pattern and the first via, the dielectric layer exposing a top surface of the first via; forming a second conductive pattern on the top surface of the first via, forming a dielectric layer covering the second conductive pattern; etching the dielectric layer to form a second through hole that exposes a portion of the second conductive pattern; forming a second via filling the second through hole and an under bump pad on the second via; and mounting a semiconductor chip on the under bump pad using a connection terminal.
